Patents by Inventor Chin Chang

Chin Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11094556
    Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ya-Wen Yeh, Yu-Tien Shen, Shih-Chun Huang, Po-Chin Chang, Wei-Liang Lin, Yung-Sung Yen, Wei-Hao Wu, Li-Te Lin, Pinyen Lin, Ru-Gun Liu
  • Patent number: 11091712
    Abstract: A method for producing biodiesel and triacetin includes steps as follows. A bio-oil source is provided; the bio-oil source is palm oil acid or palm oil sludge. A bio-oil source pretreatment step is performed, wherein the bio-oil source is mixed with ash to decolor. A pre-esterification step is performed, wherein methanol and a pre-esterification catalyst are mixed, so as to form an organic phase solution and an aqueous phase solution. A transesterification step is performed, wherein the methanol and a lithium silicate catalyst are mixed, so as to form a crude biodiesel phase solution and a crude glycerol phase solution. A washing step is performed, wherein purified biodiesel is collected. A glycerol separating step is performed, wherein purified glycerol is collected. A glycerol esterification step is performed, wherein triacetin is collected.
    Type: Grant
    Filed: March 15, 2020
    Date of Patent: August 17, 2021
    Inventor: Chin-Chang Chen
  • Publication number: 20210240906
    Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.
    Type: Application
    Filed: April 19, 2021
    Publication date: August 5, 2021
    Inventors: Rachid Salik, Chin-Chang Hsu, Cheng-Chi Wu, Chien-Wen Chen, Wen-Ju Yang
  • Publication number: 20210235370
    Abstract: A WI-FI hotspot recommendation method includes scanning a WI-FI hotspot, determining an Internet-accessible hotspot in WI-FI hotspots that are obtained by means of scanning, determining network quality obtained when the terminal accesses a network by using the Internet-accessible hotspot, and displaying an identifier of the Internet-accessible hotspot and an identifier that indicates the network quality obtained when the terminal accesses the network by using the Internet-accessible hotspot.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 29, 2021
    Inventors: Yuxin Yang, Wang Chen, Ti-Yu Wu, Te-Chin Chang, Xiuping Zhang
  • Publication number: 20210233883
    Abstract: A method of forming a semiconductor structure is provided. A layout of a substrate is provided. The layout includes a surface having an inner region and an outer region surrounding the inner region. An under bump metallurgy (UBM) pad region within the outer region is defined. The UBM pad region is partitioned into a first zone and a second zone, wherein the first zone faces towards a center of the substrate, and the second zone faces away from the center of the substrate. The substrate is provided according to the layout, wherein the providing of the substrate includes forming a conductive via in the substrate. The conductive via is disposed outside the second zone and at least partially overlaps the first zone from a top view perspective. A UBM pad is formed over the conductive via and within the UBM pad region.
    Type: Application
    Filed: April 13, 2021
    Publication date: July 29, 2021
    Inventors: KUO-CHIN CHANG, YEN-KUN LAI, KUO-CHING HSU, MIRNG-JI LII
  • Patent number: 11075880
    Abstract: This application provides a data service method relates to the field of communications technologies, the method comprises: a first router is connected to a second router, and the first router establishes a connection to the Internet. The terminal establishes a wireless local area network connection to the second router. A terminal broadcasts request information for obtaining a network configuration parameter. The terminal receives and stores a first network configuration parameter and a second network configuration parameter respectively sent by the first router and the second router; and determines a network configuration parameter used for network configuration. The second router receives a second data service request sent by the terminal, and forwards the request to the first router, so that the first router sends the request to a server through the Internet, thereby implementing a second data service of the terminal.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: July 27, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xiuping Zhang, Te-Chin Chang
  • Patent number: 11062075
    Abstract: A method of manufacturing an integrated circuit includes generating a layout design of the integrated circuit, manufacturing the integrated circuit based on the layout design, and removing a portion of a gate structure of a set of gate structures thereby forming a first and a second gate structure. Generating the layout design includes placing a set of gate layout patterns and a cut feature layout pattern on the first layout level. The cut feature layout pattern extends in a first direction, overlaps the set of gate layout patterns and identifies a location of the portion of the gate structure of the set of gate structures. The set of gate layout patterns correspond to fabricating a set of gate structures. The set of gate layout patterns extending in a second direction and overlapping a set of gridlines that extend in the second direction.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jung Chang, Chin-Chang Hsu, Hsien-Hsin Sean Lee, Wen-Ju Yang
  • Publication number: 20210197299
    Abstract: A table saw includes a base assembly; a table assembly mounted on the base assembly and comprising a table and a circular saw blade; a rip fence assembly moveably disposed on one end of the table assembly; and a slide mechanism mounted on the table assembly and including front and rear tracks affixed to front end rear ends of the table respectively; front and rear slides each having one end secured to either end of the rip fence assembly and the other end being open wherein the front and rear slides are moveably mounted on the front and rear tracks respectively; and first, second, third, fourth, and fifth rollers disposed in each of the front and rear tracks. The first, second, fourth, and fifth rollers are at an elevation higher than that of the third roller.
    Type: Application
    Filed: December 25, 2019
    Publication date: July 1, 2021
    Inventor: Chin-Chin Chang
  • Publication number: 20210199182
    Abstract: A device for adjusting tautness of a belt of a motor of a table saw is provided with an adjustment screw, and a pivot. In response to unfastening the adjustment screw, the motor counterclockwise rotates about the pivot to tighten the belt until predetermined tautness is obtained. The adjustment screw fastens to keep the belt at the predetermined tautness. Alternatively, the motor clockwise rotates about the pivot to loosen the belt.
    Type: Application
    Filed: December 25, 2019
    Publication date: July 1, 2021
    Inventor: Chin-Chin Chang
  • Patent number: 11043381
    Abstract: A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.
    Type: Grant
    Filed: January 27, 2019
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chin Chang, Li-Te Lin, Ru-Gun Liu, Wei-Liang Lin, Pinyen Lin, Yu-Tien Shen, Ya-Wen Yeh
  • Publication number: 20210176665
    Abstract: A data packet transmission method—that includes: obtaining, by a terminal, N application programs that are running; and if the N application programs include an application program including a low-latency service; determining whether an unlicensed frequency band is in a congestion state; and instructing a network device to schedule a data packet of the terminal to a licensed frequency band for transmission when the unlicensed frequency band is in a congestion state. When determining that the N running application programs include the application program including the low-latency service, the terminal may instruct the network device to schedule the data packet of the terminal to the licensed frequency band for transmission, so as to transmit a data packet of the low-latency service by using the licensed frequency band. Resources in the licensed frequency band are centrally scheduled by the network device, instead of being used through contention.
    Type: Application
    Filed: November 30, 2017
    Publication date: June 10, 2021
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: YUAN-HAO LAN, Fei YIN, Yuxin YANG, Te-Chin CHANG, HAW-WEI SHU
  • Publication number: 20210170508
    Abstract: A scale assembly of a table saw includes front and rear outer slide members disposed at front and rear ends of a slide mechanism respectively; front and rear inner slide members disposed at front and rear ends of a table assembly respectively wherein the front inner slide member slides in the front outer slide member, and the rear inner slide member slides in the rear outer slide member; a block member secured to a front end of a rip fence assembly and including a channel and a spring biased member; and a lever in the channel and including an exposed trigger, a projection, and first and second recesses. In a locked position, the spring biased member has one end entered the first recess and the projection enters a lengthwise cavity on an outer surface of the front outer slide member.
    Type: Application
    Filed: December 10, 2019
    Publication date: June 10, 2021
    Inventor: Chin-Chin Chang
  • Publication number: 20210157023
    Abstract: The present disclosure is related to a detecting device which includes a fixing component, a sensing component, and a terminal. The fixing component is fixed to an object under test and generates a first magnetic field. The sensing component includes a driving module and a reference module. The driving module generates a second magnetic field, and the driving module further generates a sensing signal according to an electromagnetic induction produced by the first magnetic field and the second magnetic field. The reference module is spaced from the driving module by a distance, such that the reference module is outside of the second magnetic field and generates a reference signal. The terminal produces detection information according to the sensing signal and the reference signal.
    Type: Application
    Filed: July 28, 2020
    Publication date: May 27, 2021
    Inventors: Min-Chun PAN, Wei-Hao LEE, Po-Chin CHANG, Tsung-Hsuan SU
  • Patent number: 11018099
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a semiconductor chip; a substrate facing an active surface of the semiconductor chip; and a conductive bump extending from the active surface of the semiconductor chip toward the substrate, wherein the conductive bump comprises: a plurality of bump segments comprising a first group of bump segments and a second group of bump segments, wherein each bump segment comprises the same segment height in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment comprises a volume defined by the multiplication of the segment height with the average cross-sectional area of the bump segment; wherein the ratio of the total volume of the first group of bump segments to the total volume of the second group of bump segments is between about 0.03 and about 0.8.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pei-Haw Tsao, An-Tai Xu, Huang-Ting Hsiao, Kuo-Chin Chang
  • Patent number: 11017148
    Abstract: A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a spacing between the conductive lines less than an acceptable minimum distance. Kn+1 graph comprising a first set of vertices selected from the plurality of vertices connected in series by a first set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the first set of vertices is reduced by merging a third vertex into a fourth vertex selected from the first set of the plurality of vertices. An n-pattern conflict check is performed and the photomasks generated based on the result.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nien-Yu Tsai, Chin-Chang Hsu, Wen-Ju Preet Yang, Hsien-Hsin Sean Lee
  • Patent number: 11009971
    Abstract: An input device includes a wheel supporting structure, a scroll wheel, a hook part, a linking part, and a switching mechanism. The scroll wheel is rotatably supported by the wheel supporting structure, is exposed from the input device, and has a rotary shaft with a plurality of toothed slots thereon. The hook part is disposed biased on the wheel supporting structure to selectively engage with the toothed slots. The linking part is pivotally connected to the wheel supporting structure. The switching mechanism includes an abutting part and a switching part. The abutting part abuts against the linking part. The switching part is coupled to the abutting part. Therein, the switching mechanism is operable to move the abutting part through the switching part to rotate the linking part to abut against and move the hook part to disengage from the toothed slots.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: May 18, 2021
    Assignee: DARFON ELECTRONICS CORP.
    Inventors: Ching-Chin Chang, Wen-Yu Tsai, Feng-Wei Su, Chun-Chieh Chen
  • Patent number: 11010529
    Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Rachid Salik, Chin-Chang Hsu, Cheng-Chi Wu, Chien-Wen Chen, Wen-Ju Yang
  • Patent number: 10998421
    Abstract: A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chin Chang, Wei-Hao Wu, Li-Te Lin, Pinyen Lin
  • Publication number: 20210124994
    Abstract: System that facilitates rapid onboarding of an autonomous (cashier-less) store by capturing images of the store's items from multiple angles, with varying backgrounds, and that builds a classifier training dataset from these images. The system may have cameras in different positions, and backgrounds that generate different background colors. It may have a platform for items that can be switched between a transparent and non-transparent state; cameras below the platform may therefore capture images of the bottom side of the item when the platform is transparent. When an item is placed in the imaging system, a fully automated process may generate a sequence of background colors and may capture and process images from all of the cameras to create training images. Images of the item from multiple angles, including views of the entire external surface of the item, may be captured without requiring an operator to move or reorient the item.
    Type: Application
    Filed: April 14, 2020
    Publication date: April 29, 2021
    Applicant: ACCEL ROBOTICS CORPORATION
    Inventors: Marius BUIBAS, John QUINN, Tanuj PANKAJ, Chin-Chang KUO
  • Publication number: 20210118767
    Abstract: A method for forming a chip package structure is provided. The method includes disposing a chip over a substrate. The method includes forming a heat-spreading wall structure over the substrate. The heat-spreading wall structure is adjacent to the chip, and there is a first gap between the chip and the heat-spreading wall structure. The method includes forming a first heat conductive layer in the first gap. The method includes forming a second heat conductive layer over the chip. The method includes disposing a heat-spreading lid over the substrate to cover the heat-spreading wall structure, the first heat conductive layer, the second heat conductive layer, and the chip. The heat-spreading lid is bonded to the substrate, the heat-spreading wall structure, the first heat conductive layer, and the second heat conductive layer.
    Type: Application
    Filed: October 16, 2019
    Publication date: April 22, 2021
    Inventors: Shin CHI, Chien-Hao HSU, Kuo-Chin CHANG, Cheng-Nan LIN, Mirng-Ji LII