Patents by Inventor Chin-Cheng Kuo
Chin-Cheng Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10169507Abstract: An integration circuit (IC) simulation method includes: (a) providing a design netlist of a system-level circuit, wherein the system-level circuit comprises a first sub-circuit; (b) providing a first behavior model that is determined based on an operation of the first sub-circuit, wherein the first behavior model is a function of one or more respective behavior-level parameters; (c) incorporating a first variation into each of the one or more behavior-level parameters of the first behavioral model; and (d) simulating the system-level circuit based on the one or more behavior-level parameters of the first behavior model that incorporates the first variation.Type: GrantFiled: February 22, 2017Date of Patent: January 1, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Cheng Kuo, Wei-Yi Hu
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Patent number: 10083257Abstract: A method includes determining a sampling region in a sample space, generating samples in the sampling region without generating samples outside the sampling region, and simulating a performance of a device using the generated samples as input data. The sample space is defined by a plurality of variables associated with the device. Values of the plurality of variables in the sampling region having lower probabilities to meet a specification of the device than values of the plurality of variables outside the sampling region. The method is performed at least partially by at least one processor.Type: GrantFiled: August 20, 2014Date of Patent: September 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Cheng Kuo, Wei Min Chan, Wei-Yu Hu, Jui-Feng Kuan
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Patent number: 10019540Abstract: A method is disclosed that includes performing a first simulation by applying first variations to identify at least one sample of an integrated circuit (IC), wherein the IC comprises at least one device; translating individual variables of split devices implementing the at least one device, to an equivalent variable for the split devices; and performing a second simulation, by applying at least a portion of second variations, with the equivalent variable for the split devices, to obtain a simulation result serving as a basis of modifying the layout for fabrication of the IC.Type: GrantFiled: December 30, 2015Date of Patent: July 10, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Cheng Kuo, Wei-Yi Hu, Kuang-Ming Wang
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Publication number: 20180164629Abstract: A display device includes a display panel, a circuit connecting board, a plurality of passive components and a first insulation layer. The circuit connecting board is connected to the display panel and has a component configuration area. The passive components are disposed on the component configuration area and include a first passive component. The first insulation layer is disposed on the component configuration area and covers the first passive component. The adhesive can be applied on the component configuration area by an automatic dispensing machine, and the adhesive is solidified to form the first insulation layer for covering the passive components. This configuration can prevent the short circuit between the metal material and the components disposed on the component configuration area of the circuit connecting board, thereby benefitting in automatically manufacturing and decreasing the production cost.Type: ApplicationFiled: December 5, 2017Publication date: June 14, 2018Inventors: Hung-Yi Lin, Chia-Chun Yang, Chin-Cheng Kuo
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Publication number: 20180150577Abstract: An integration circuit (IC) simulation method includes: (a) providing a design netlist of a system-level circuit, wherein the system-level circuit comprises a first sub-circuit; (b) providing a first behavior model that is determined based on an operation of the first sub-circuit, wherein the first behavior model is a function of one or more respective behavior-level parameters; (c) incorporating a first variation into each of the one or more behavior-level parameters of the first behavioral model; and (d) simulating the system-level circuit based on the one or more behavior-level parameters of the first behavior model that incorporates the first variation.Type: ApplicationFiled: February 22, 2017Publication date: May 31, 2018Inventors: Chin-Cheng KUO, Wei-Yi HU
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Publication number: 20180149808Abstract: A display device and a method for preparing the same are disclosed. The display device includes a display panel and a backlight module. The backlight module is located below the display panel and includes a back plate, a first adhesive layer, a light emitting module and a reflector. The first adhesive layer is disposed on the back plate and the first adhesive layer includes a first area and a second area. The first area is adjacent to the second area. The light emitting module includes a light emitting unit and a print circuit board. The light emitting unit and the print circuit board are electrically connected, and the print circuit board is disposed in the first area of the first adhesive layer. A part of the reflector is disposed in the second area of the first adhesive layer.Type: ApplicationFiled: November 20, 2017Publication date: May 31, 2018Inventors: Chih-Chiao YANG, Chia-Chun YANG, Chin-Cheng KUO, Jia-Sin LI
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Publication number: 20180143372Abstract: A display module is provided. The display module includes a backlight module with an upper surface, a display panel opposite to the backlight module, and a glue having a first contact surface and a second contact surface located between the display panel and the backlight module, wherein the first contact surface is in contact with the display panel, the second contact surface is in contact with the upper surface of the backlight module, and there is a gap between the display panel and the backlight module. A method for fabricating a display module is also provided.Type: ApplicationFiled: November 20, 2017Publication date: May 24, 2018Inventors: Li-Ling CHEN, Chien-Chih CHEN, Chia-Chun YANG, Chin-Cheng KUO
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Publication number: 20180143487Abstract: A display device includes a display panel, a light shielding unit, a supporting unit, and a backlight module. The display panel includes a first substrate and a first polarizer. The first substrate has a first surface, and the first surface has a first active area and a first non-active area. The first non-active area is disposed adjacent to the first active area, and the first polarizer is disposed on the first active area. The light shielding unit is disposed on the first non-active area and connected to the first polarizer. The supporting unit is disposed corresponding to the light shielding unit. The backlight module is disposed corresponding to the display panel and includes an optical film. The supporting unit is disposed between the light shielding unit and the optical film, and contacts the light shielding unit and the optical film.Type: ApplicationFiled: October 25, 2017Publication date: May 24, 2018Inventors: Chien-Chih CHEN, Chia-Chun YANG, Chin-Cheng KUO, Hsin-Tien WU, Chih-Jen CHANG
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Publication number: 20180146555Abstract: A display device and a manufacturing method thereof are provided. The display device includes a first substrate, a second substrate, a drive IC and a protection layer. The first substrate has a first region and a second region. The second substrate is correspondingly disposed on the first region. The drive IC is disposed on the second region. The protection layer is disposed enclosing the drive IC, and the protection layer has a maximum height larger than the height of the drive IC.Type: ApplicationFiled: October 30, 2017Publication date: May 24, 2018Inventors: Chin-Cheng Kuo, Chia-Chun Yang, Wen-Cheng Huang
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Publication number: 20180122749Abstract: A semiconductor wafer includes a substrate structure, a first insulation layer, a conductive layer and a second insulation layer. The substrate structure defines a via. The first insulation layer covers a surface of the substrate structure. The first insulation layer extends into the via, covers a lateral wall of the via and exposes a bottom surface at a bottom of the via. The conductive layer covers the first insulation layer and the bottom surface exposed by the first insulation layer. The second insulation layer covers the conductive layer. A warpage of the semiconductor wafer is less than 550 micrometers.Type: ApplicationFiled: November 1, 2016Publication date: May 3, 2018Inventors: Ying-Chih LEE, Chin-Cheng KUO, Yung-Hui WANG, Wei-Hong LAI, Chung-Ting WANG, Hsiao-Yen LEE
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Publication number: 20170365515Abstract: The present disclosure relates to a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a semiconductor substrate having a first surface and a second surface opposite the first surface. The semiconductor substrate has a space extending from the second surface to the first surface and an insulation body is disposed in the space. The semiconductor package structure includes conductive posts in the insulation body.Type: ApplicationFiled: June 16, 2016Publication date: December 21, 2017Inventors: Chin-Cheng KUO, Pao-Nan LEE, Chih-Pin HUNG, Ying-Te OU
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Publication number: 20170287863Abstract: A semiconductor die includes a semiconductor body, an insulating layer, a conductive circuit layer and at least one conductive bump. The semiconductor body has a first surface, a second surface and a side surface extending between the first surface and the second surface. The insulating layer is disposed on the first surface and the side surface of the semiconductor body. The insulating layer includes a first insulating layer over the semiconductor body and a second insulating layer over the first insulating later. The insulating layer includes a step structure. The conductive circuit layer is electrically connected to the first surface of the semiconductor body, the conductive circuit layer includes at least one pad, and the conductive bump is electrically connected to the pad.Type: ApplicationFiled: June 20, 2017Publication date: October 5, 2017Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chin-Cheng KUO, Ying-Te OU, Lu-Ming LAI
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Patent number: 9753895Abstract: A method and a corresponding system for process variation analysis of an integrated circuit are provided. A netlist is generated describing electronic devices of an integrated circuit in terms of device parameters and process parameters. The process parameters include local process parameters individual to the electronic devices and global process parameters common to the electronic devices. Critical electronic devices are identified having device parameters with greatest contributions to a performance parameter of a design specification of the integrated circuit. Sensitivity values are determined for the global process parameters and local process parameters of the critical electronic devices. The sensitivity values represent how sensitive the one or more performance parameters are to variations in the global and local process parameters of the critical electronic devices. Monte Carlo (MC) samples are sorted based on the sensitivity values.Type: GrantFiled: August 5, 2015Date of Patent: September 5, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Cheng Kuo, Kmin Hsu, Wei-Yi Hu, Wei Min Chan, Jui-Feng Kuan
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Patent number: 9711473Abstract: A semiconductor die includes a semiconductor body, an insulating layer, a conductive circuit layer and at least one conductive bump. The semiconductor body has a first surface, a second surface and a side surface extending between the first surface and the second surface. The insulating layer is disposed on the first surface and the side surface of the semiconductor body. The insulating layer includes a first insulating layer over the semiconductor body and a second insulating layer over the first insulating later. The insulating layer includes a step structure. The conductive circuit layer is electrically connected to the first surface of the semiconductor body, the conductive circuit layer includes at least one pad, and the conductive bump is electrically connected to the pad.Type: GrantFiled: February 26, 2016Date of Patent: July 18, 2017Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chin-Cheng Kuo, Ying-Te Ou, Lu-Ming Lai
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Publication number: 20170193139Abstract: A method is disclosed that includes performing a first simulation by applying first variations to identify at least one sample of an integrated circuit (IC), wherein the IC comprises at least one device; translating individual variables of split devices implementing the at least one device, to an equivalent variable for the split devices; and performing a second simulation, by applying at least a portion of second variations, with the equivalent variable for the split devices, to obtain a simulation result serving as a basis of modifying the layout for fabrication of the IC.Type: ApplicationFiled: December 30, 2015Publication date: July 6, 2017Inventors: Chin-Cheng Kuo, Wei-Yi Hu, Kuang-Ming Wang
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Patent number: 9519735Abstract: In some methods, a number of input data sets is provided for an integrated circuit (IC) model. A number of scores for the number of input data sets, respectively, are then determined based on probabilities of the respective input data sets resulting in a failure condition, which exists when the IC model fails to meet a predetermined yield criteria. A simulation order for the number of input data sets is then assigned according to the determined number of scores.Type: GrantFiled: September 22, 2014Date of Patent: December 13, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Cheng Kuo, Kmin Hsu, Wei-Yi Hu, Wei Min Chan, Jui-Feng Kuan
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Publication number: 20160055273Abstract: A method includes determining a sampling region in a sample space, generating samples in the sampling region without generating samples outside the sampling region, and simulating a performance of a device using the generated samples as input data. The sample space is defined by a plurality of variables associated with the device. Values of the plurality of variables in the sampling region having lower probabilities to meet a specification of the device than values of the plurality of variables outside the sampling region. The method is performed at least partially by at least one processor.Type: ApplicationFiled: August 20, 2014Publication date: February 25, 2016Inventors: Chin-Cheng KUO, Wei Min CHAN, Wei-Yu HU, Jui-Feng KUAN
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Publication number: 20150339414Abstract: A method and a corresponding system for process variation analysis of an integrated circuit are provided. A netlist is generated describing electronic devices of an integrated circuit in terms of device parameters and process parameters. The process parameters include local process parameters individual to the electronic devices and global process parameters common to the electronic devices. Critical electronic devices are identified having device parameters with greatest contributions to a performance parameter of a design specification of the integrated circuit. Sensitivity values are determined for the global process parameters and local process parameters of the critical electronic devices. The sensitivity values represent how sensitive the one or more performance parameters are to variations in the global and local process parameters of the critical electronic devices. Monte Carlo (MC) samples are sorted based on the sensitivity values.Type: ApplicationFiled: August 5, 2015Publication date: November 26, 2015Inventors: Chin-Cheng Kuo, Kmin Hsu, Wei-Yi Hu, Wei Min Chan, Jui-Feng Kuan
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Publication number: 20150089463Abstract: In some methods, a number of input data sets is provided for an integrated circuit (IC) model. A number of scores for the number of input data sets, respectively, are then determined based on probabilities of the respective input data sets resulting in a failure condition, which exists when the IC model fails to meet a predetermined yield criteria. A simulation order for the number of input data sets is then assigned according to the determined number of scores.Type: ApplicationFiled: September 22, 2014Publication date: March 26, 2015Inventors: Chin-Cheng Kuo, Kmin Hsu, Wei-Yi Hu, Wei Min Chan, Jui-Feng Kuan
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Patent number: 8707230Abstract: An integrated circuit (IC) simulation method comprises providing a device process model from a non-transitory machine readable storage medium into a programmed computer. The device process model includes one or more device variables. Each device variable defines a probability distribution of an active-device-level variation of devices in an IC. A conductive line model and/or a multi patterning technology (MPT) model is provided from the storage medium to the computer. The conductive line model includes one or more conductive line variables. Each conductive line variable defines a probability distribution of a conductive-line process-induced variation. The MPT model includes one or more MPT variables. Each MPT variable defines a probability distribution of a mask-misalignment-induced conductive line coupling variation. A Monte Carlo simulation is performed in the computer, including the device process model and the conductive line model or MPT model, to identify parasitic couplings in the IC.Type: GrantFiled: March 11, 2013Date of Patent: April 22, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Yi Hu, Chin-Cheng Kuo, Cheng-Hung Yeh, Jui-Feng Kuan, Yi-Kan Cheng