Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect within a first inter-level dielectric (ILD) layer over a substrate. A memory device is disposed over the first interconnect and is surrounded by a second ILD layer. A sidewall spacer is arranged along opposing sides of the memory device and an etch stop layer is arranged on the sidewall spacer. The sidewall spacer and the etch stop layer have upper surfaces that are vertically offset from one another by a non-zero distance. A second interconnect extends from a top of the second ILD layer to an upper surface of the memory device.

Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain has a zero-tilt doping profile and the source has a tilted doping profile. The resistive memory element is coupled with the drain via a portion of an interconnect structure.

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element and a second RRAM element over a substrate. A conductive element is arranged below the first RRAM element and the second RRAM element. The conductive element electrically couples the first RRAM element to the second RRAM element. An upper insulating layer continuously extends over the first RRAM element and the second RRAM element. An upper inter-level dielectric (ILD) structure laterally surrounds the first RRAM element and the second RRAM element. The upper insulating layer separates the first RRAM element and the second RRAM element from the upper ILD structure.

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element over a substrate. The first RRAM element has a first terminal and a second terminal. A second RRAM element is arranged over the substrate and has a third terminal and a fourth terminal. The third terminal is electrically coupled to the first terminal of the first RRAM element. A reading circuit is coupled to the second terminal and the fourth terminal. The reading circuit is configured to read a single data state from both a first non-zero read current received from the first RRAM element and a second non-zero read current received from the second RRAM element.

Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.

Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) cell. The RRAM cell has a bottom electrode over a substrate. A data storage layer is over the bottom electrode and has a first thickness. A capping layer is over the data storage layer. The capping layer has a second thickness that is in a range of between approximately 1.9 and approximately 3 times thicker than the first thickness. A top electrode is over the capping layer.

Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.

Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain has a zero-tilt doping profile and the source has a tilted doping profile. The resistive memory element is coupled with the drain via a portion of an interconnect structure.

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element over a substrate. The first RRAM element has a first terminal and a second terminal. A second RRAM element is arranged over the substrate and has a third terminal and a fourth terminal. The third terminal is electrically coupled to the first terminal of the first RRAM element. A reading circuit is coupled to the second terminal and the fourth terminal. The reading circuit is configured to read a single data state from both a first non-zero read current received from the first RRAM element and a second non-zero read current received from the second RRAM element.

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain has a zero-tilt doping profile and the source has a tilted doping profile. The resistive memory element is coupled with the drain via a portion of an interconnect structure.

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a conductive element disposed within a dielectric structure over the substrate. The conductive element has a top surface extend between outermost sidewalls of the conductive element. A first resistive random access memory (RRAM) element is arranged within the dielectric structure and has a first data storage layer directly contacting the top surface of the conductive element. A second RRAM element is arranged within the dielectric structure and has a second data storage layer directly contacting the top surface of the conductive element.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect within a first inter-level dielectric (ILD) layer over a substrate. A memory device is disposed over the first interconnect and is surrounded by a second ILD layer. A sidewall spacer is arranged along opposing sides of the memory device and an etch stop layer is arranged on the sidewall spacer. The sidewall spacer and the etch stop layer have upper surfaces that are vertically offset from one another by a non-zero distance. A second interconnect extends from a top of the second ILD layer to an upper surface of the memory device.