Patents by Inventor Chin-Chieh YANG

Chin-Chieh YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9876167
    Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a good yield, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer, and forming a variable resistance dielectric data storage layer having a first thickness onto the bottom electrode. A capping layer is formed onto the dielectric data storage layer. The capping layer has a second thickness that is in a range of between approximately 2 to approximately 3 times thicker than the first thickness. A top electrode is formed over the capping layer, and an upper metal interconnect layer is formed over the top electrode.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: January 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Trinh Hai Dang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chin-Chieh Yang, Yu-Wen Liao, Wen-Ting Chu, Chia-Shiung Tsai
  • Publication number: 20180019390
    Abstract: Some embodiments relate to an integrated circuit device, which includes a bottom electrode, a dielectric layer, and top electrode. The dielectric layer is disposed over the bottom electrode. The top electrode is disposed over the dielectric layer, and an upper surface of the top electrode exhibits a recess. A via is disposed over the top electrode. The via makes electrical contact with only a tapered sidewall of the recess without contacting a bottom surface of the recess.
    Type: Application
    Filed: September 26, 2017
    Publication date: January 18, 2018
    Inventors: Hsia-Wei Chen, Wen-Ting Chu, Kuo-Chi Tu, Chih-Yang Chang, Chin-Chieh Yang, Yu-Wen Liao, Wen-Chun You, Sheng-Hung Shih
  • Publication number: 20180012657
    Abstract: In some embodiments, the present disclosure relates to a method of operating an RRAM cell having a PMOS access transistor. The method may be performed by turning on a PMOS transistor having a drain terminal coupled to a lower electrode of an RRAM device. A first voltage is provided to a source terminal of the PMOS transistor, and a second voltage is provided to a bulk terminal of the PMOS transistor. The second voltage is larger than the first voltage. A third voltage is provided to an upper electrode of the RRAM device. The third voltage is larger than the first voltage.
    Type: Application
    Filed: September 12, 2017
    Publication date: January 11, 2018
    Inventors: Sheng-Hung Shih, Kuo-Chi Tu, Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang, Jen-Sheng Yang, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 9853213
    Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: December 26, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 9818938
    Abstract: A method of forming a semiconductor structure includes depositing a first electrode material over a conductive structure and a dielectric layer, patterning the first electrode material to form a first electrode contacting the conductive structure, depositing a resistance variable layer over the first electrode and the dielectric layer, depositing a second electrode material over the resistance variable layer, and etching a portion of the second electrode material and the resistance variable layer to form a second electrode over a remaining portion of the resistance variable layer.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Kuo-Chi Tu, Chih-Yang Chang, Hsia-Wei Chen, Yu-Wen Liao, Chin-Chieh Yang, Wen-Ting Chu
  • Publication number: 20170317143
    Abstract: The present disclosure relates to an integrated circuit having an interconnect wire contacting an upper electrode of the RRAM (resistive random access memory) device, and a method of formation. In some embodiments, the integrated circuit comprises an RRAM device having a dielectric data storage layer disposed between a lower electrode and an upper electrode. An interconnect wire contacts an upper surface of the upper electrode, and an interconnect via is arranged onto the interconnect wire. The interconnect via is set back from one or more outermost sidewalls of the interconnect wire. The interconnect wire has a relatively large size that provides for a good electrical connection between the interconnect wire and the upper electrode, thereby increasing a process window of the RRAM device.
    Type: Application
    Filed: February 24, 2017
    Publication date: November 2, 2017
    Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 9780145
    Abstract: A resistive random access memory (RRAM) cell comprises a transistor having a gate and a source/drain region, a bottom electrode coplanar with the gate, a resistive material layer over the bottom electrode, a top electrode over the resistive material layer, and a conductive material electrically connecting the bottom electrode to the source/drain region.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: October 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yang Chang, Wen-Ting Chu, Kuo-Chi Tu, Yu-Wen Liao, Hsia-Wei Chen, Chin-Chieh Yang
  • Patent number: 9780302
    Abstract: Some embodiments relate to an integrated circuit device. The integrated circuit device includes a resistive random access memory (RRAM) cell, which includes a top electrode and a bottom electrode that are separated by a RRAM dielectric layer. The top electrode of the RRAM cell has a recess in its upper surface. A via is disposed over the RRAM cell and contacts the top electrode within the recess.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: October 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsia-Wei Chen, Wen-Ting Chu, Kuo-Chi Tu, Chih-Yang Chang, Chin-Chieh Yang, Yu-Wen Liao, Wen-Chun You, Sheng-Hung Shih
  • Patent number: 9773552
    Abstract: In some embodiments, the present disclosure relates to a method of operating an RRAM cell having a PMOS access transistor. The method may be performed by forming an initial conductive filament within a dielectric data storage layer of an RRAM cell having a bottom electrode connected to a drain terminal of a PMOS transistor and a top electrode separated from the bottom electrode by the dielectric data storage layer. The initial conductive filament is formed by turning on the PMOS transistor by providing a substantially zero first forming voltage to a gate terminal of the PMOS transistor, by providing a substantially zero second forming voltage to a source terminal of the PMOS transistor, by providing a first non-zero forming voltage to a bulk terminal of the PMOS transistor, and by providing a second non-zero forming voltage to the top electrode.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hung Shih, Kuo-Chi Tu, Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang, Jen-Sheng Yang, Wen-Ting Chu, Yu-Wen Liao
  • Publication number: 20170271590
    Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, a protection material and a second electrode. The first electrode has a top surface on the memory region. The resistance variable layer has at least a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection material surrounds the second portion of the resistance variable layer. The protection material is configurable to protect at least one conductive path in the resistance variable layer. The second electrode is disposed over the resistance variable layer.
    Type: Application
    Filed: June 5, 2017
    Publication date: September 21, 2017
    Inventors: Kuo-Chi Tu, Chih-Yang CHANG, Hsia-Wei CHEN, Yu-Wen LIAO, Chin-Chieh YANG, Wen-Ting CHU
  • Publication number: 20170236581
    Abstract: The present disclosure relates to a method and apparatus for performing a read operation of an RRAM cell, which applies a non-zero bias voltage to unselected bit-lines and select-lines to increase a read current window without damaging corresponding access transistors. In some embodiments, the method may be performed by activating a word-line coupled to a row of RRAM cells comprising a selected RRAM device by applying a first read voltage to the word-line. A second read voltage is applied to a bit-line coupled to a first electrode of the selected RRAM device. One or more non-zero bias voltages are applied to bit-lines and select-lines coupled to RRAM cells, within the row of RRAM cells, having unselected RRAM devices.
    Type: Application
    Filed: February 6, 2017
    Publication date: August 17, 2017
    Inventors: Chin-Chieh Yang, Chih-Yang Chang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Manish Kumar Singh, Chi-Tsai Chen
  • Publication number: 20170207387
    Abstract: The present disclosure relates to an integrated circuit, which includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a lower metal layer, an intermediate metal layer disposed over the lower metal layer, and an upper metal layer disposed over the intermediate metal layer. An upper surface of the lower metal layer and a lower surface of the intermediate metal layer are spaced vertically apart by a first distance. A resistive random access memory (RRAM) cell is arranged between the lower metal layer and the upper metal layer. The RRAM cell includes a bottom electrode and a top electrode which are separated by a data storage layer having a variable resistance. The data storage layer vertically spans a second distance that is greater than the first distance.
    Type: Application
    Filed: January 11, 2017
    Publication date: July 20, 2017
    Inventors: Jen-Sheng Yang, Chih-Yang Chang, Chin-Chieh Yang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Yu-Wen Liao, Manish Kumar Singh
  • Patent number: 9673391
    Abstract: A method includes forming a protection material over a conductive structure, an opening over the structure is partially filled with a first electrode material to form a first electrode; a resistance variable layer and a second electrode material are also formed in the opening. The second electrode material and the resistance variable layer are patterned to form a memory element. The method includes forming an interlayer dielectric over the memory element and the periphery region of the substrate and disposing contacts in the interlayer dielectric.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chi Tu, Chih-Yang Chang, Hsia-Wei Chen, Yu-Wen Liao, Chin-Chieh Yang, Wen-Ting Chu
  • Publication number: 20170141026
    Abstract: The present disclosure relates to an integrated circuit configured to mitigate damage to MIM decoupling capacitors. In some embodiments, the integrated chip has a lower metal interconnect layer arranged over a substrate. A plurality of MIM (metal-insulator-metal) structures are arranged over the lower metal interconnect layer, and a plurality of memory cells are arranged over the lower metal interconnect layer at a location laterally offset from the plurality of MIM structures. An upper metal interconnect layer is arranged over the plurality of MIM structures and the plurality of memory cells. One or both of the lower metal interconnect layer and the upper metal interconnect layer are comprised within a conductive path that electrically couples the plurality of MIM structures in a series connection. The plurality of MIM structures and the plurality of memory cells comprise multi-layer structures having a substantially same shape.
    Type: Application
    Filed: January 30, 2017
    Publication date: May 18, 2017
    Inventors: Kuo-Chi Tu, Chin-Chieh Yang, Wen-Ting Chu
  • Publication number: 20170141301
    Abstract: The present disclosure relates to a resistive random access memory (RRAM) device. The RRAM device has a bottom electrode arranged over a bottom electrode via. A variable resistive dielectric layer is arranged over the bottom electrode. The variable resistive dielectric layer extends to within a recess in an upper surface of the bottom electrode. A top electrode is disposed over the variable resistive dielectric layer. A top electrode via extends outward from an upper surface of the top electrode at a position centered along a first axis that is laterally offset from a second axis centered upon the recess within the upper surface of the bottom electrode.
    Type: Application
    Filed: July 29, 2016
    Publication date: May 18, 2017
    Inventors: Chih-Yang Chang, Wen-Ting Chu, Kuo-Chi Tu, Yu-Wen Liao, Hsia-Wei Chen, Chin-Chieh Yang, Sheng-Hung Shih, Wen-Chun You
  • Publication number: 20170140820
    Abstract: In some embodiments, the present disclosure relates to a method of operating an RRAM cell having a PMOS access transistor. The method may be performed by forming an initial conductive filament within a dielectric data storage layer of an RRAM cell having a bottom electrode connected to a drain terminal of a PMOS transistor and a top electrode separated from the bottom electrode by the dielectric data storage layer. The initial conductive filament is formed by turning on the PMOS transistor by providing a substantially zero first forming voltage to a gate terminal of the PMOS transistor, by providing a substantially zero second forming voltage to a source terminal of the PMOS transistor, by providing a first non-zero forming voltage to a bulk terminal of the PMOS transistor, and by providing a second non-zero forming voltage to the top electrode.
    Type: Application
    Filed: January 6, 2017
    Publication date: May 18, 2017
    Inventors: Sheng-Hung Shih, Kuo-Chi Tu, Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang, Jen-Sheng Yang, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 9647207
    Abstract: A resistive random access memory (RRAM) cell with a high ? layer based on a group-V oxide and hafnium oxide is provided. The RRAM cell includes a bottom electrode layer, a group-V oxide layer arranged over the bottom electrode layer, and a hafnium oxide based layer arranged over and abutting the group-V oxide layer. The RRAM cell further includes a capping layer arranged over and abutting the hafnium oxide based layer, and a top electrode layer arranged over the capping layer. A method for manufacturing the RRAM cell is also provided.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: May 9, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hai-Dang Trinh, Chia-Shiung Tsai, Chin-Wei Liang, Cheng-Yuan Tsai, Hsing-Lien Lin, Chin-Chieh Yang, Wen-Ting Chu
  • Publication number: 20170098764
    Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.
    Type: Application
    Filed: December 15, 2016
    Publication date: April 6, 2017
    Inventors: Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 9601545
    Abstract: The present disclosure relates to a method of forming an integrated circuit that prevents damage to MIM decoupling capacitors, and an associated structure. In some embodiments, the method comprises forming one or more lower metal interconnect structures within a lower ILD layer over a substrate. A plurality of MIM structures are formed over the lower metal interconnect structures, and one or more upper metal interconnect structures are formed within an upper ILD layer over the plurality of MIM structures. Together the lower and upper metal interconnect structures electrically couple the plurality of MIM structures in a series connection between a first voltage potential and a second voltage potential. By placing the MIM structures in a series connection, dissipation of the first voltage potential (e.g., a supply voltage) is spread out over the MIM structures, thereby reducing the voltage potential difference between electrodes of any one of the MIM structures.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Chi Tu, Chin-Chieh Yang, Wen-Ting Chu
  • Patent number: 9577009
    Abstract: The present disclosure relates to an integrated chip comprising an RRAM cell that is driven by a PMOS transistor, and an associated method of formation. In some embodiments, the integrated chip has a PMOS transistor arranged within a semiconductor substrate. A resistive RRAM cell is arranged within an inter-level dielectric (ILD) layer overlying the semiconductor substrate. The RRAM cell has a first conductive electrode separated from a second conductive electrode by a dielectric data storage layer having a variable resistance. The first conductive electrode is connected to a drain terminal of the PMOS transistor by one or more metal interconnect layers. The use of a PMOS transistor to drive the RRAM cell allows for impact of the body effect to be reduced and therefore allows for a reset operation to be performed at a low power and in a short amount of time.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hung Shih, Kuo-Chi Tu, Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang, Jen-Sheng Yang, Wen-Ting Chu, Yu-Wen Liao