Patents by Inventor Chin-Hsiang Lin
Chin-Hsiang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12222647Abstract: A photoresist composition includes a conjugated resist additive, a photoactive compound, and a polymer resin. The conjugated resist additive is one or more selected from the group consisting of a polyacetylene, a polythiophene, a polyphenylenevinylene, a polyfluorene, a polypryrrole, a polyphenylene, and a polyaniline. The polyacetylene, polythiophene, polyphenylenevinylene, polyfluorene, polypryrrole, the polyphenylene, and polyaniline includes a substituent selected from the group consisting of an alkyl group, an ether group, an ester group, an alkene group, an aromatic group, an anthracene group, an alcohol group, an amine group, a carboxylic acid group, and an amide group. Another photoresist composition includes a polymer resin having a conjugated moiety and a photoactive compound. The conjugated moiety is one or more selected from the group consisting of a polyacetylene, a polythiophene, a polyphenylenevinylene, a polyfluorene, a polypryrrole, a polyphenylene, and a polyaniline.Type: GrantFiled: July 25, 2022Date of Patent: February 11, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Chih Ho, Ching-Yu Chang, Chin-Hsiang Lin
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Patent number: 12222654Abstract: A method includes illuminating radiation to a resist layer over a substrate to pattern the resist layer. The patterned resist layer is developed by using a positive tone developer. The patterned resist layer is rinsed using a basic aqueous rinse solution. A pH value of the basic aqueous rinse solution is lower than a pH value of the developer, and a rinse temperature of rinsing the patterned resist layer is in a range of about 20° C. to about 40° C.Type: GrantFiled: July 16, 2021Date of Patent: February 11, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Hui Weng, Chen-Yu Liu, Cheng-Han Wu, Ching-Yu Chang, Chin-Hsiang Lin
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Patent number: 12222653Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a resist layer over a material layer, the resist layer includes an inorganic material. The inorganic material includes a plurality of metallic cores and a plurality of first linkers bonded to the metallic cores. The method includes forming a modified layer over the resist layer, and the modified layer includes an auxiliary. The method includes performing an exposure process on the modified layer and the resist layer, and removing a portion of the modified layer and a first portion of the resist layer by a first developer. The first developer includes a ketone-based solvent having a substituted or unsubstituted C6-C7 cyclic ketone, an ester-based solvent having a formula (b), or a combination thereof.Type: GrantFiled: May 14, 2021Date of Patent: February 11, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Hui Weng, An-Ren Zi, Ching-Yu Chang, Chin-Hsiang Lin, Chen-Yu Liu
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Patent number: 12211751Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.Type: GrantFiled: December 28, 2023Date of Patent: January 28, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
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Patent number: 12211698Abstract: Provided is a material composition and method that includes forming a patterned resist layer on a substrate, where the patterned resist layer has a first line width roughness. In various embodiments, the patterned resist layer is coated with a treatment material, where a first portion of the treatment material bonds to surfaces of the patterned resist layer. In some embodiments, a second portion of the treatment material (e.g., not bonded to surfaces of the patterned resist layer) is removed, thereby providing a treated patterned resist layer, where the treated patterned resist layer has a second line width roughness less than the first line width roughness.Type: GrantFiled: June 1, 2020Date of Patent: January 28, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Siao-Shan Wang, Cheng-Han Wu, Ching-Yu Chang, Chin-Hsiang Lin
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Patent number: 12181798Abstract: The present disclosure provides a method for lithography patterning in accordance with some embodiments. The method includes forming a photoresist layer over a substrate, wherein the photoresist layer includes a metal-containing chemical; performing an exposing process to the photoresist layer; and performing a first developing process to the photoresist layer using a first developer, thereby forming a patterned resist layer, wherein the first developer includes a first solvent and a chemical additive to remove metal residuals generated from the metal-containing chemical.Type: GrantFiled: August 9, 2023Date of Patent: December 31, 2024Assignee: TAIWAIN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: An-Ren Zi, Joy Cheng, Ching-Yu Chang, Chin-Hsiang Lin
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Publication number: 20240419069Abstract: A method for forming a semiconductor device is provided. The method includes forming a photoresist layer comprising an organometallic compound over a substrate. The organometallic compound includes a metal core, at least one hydrolyzable ligand bonded to the metal core, and at least one photoacid generator ligand bonded to the metal core. The method further includes selectively exposing the photoresist layer to radiation and developing the photoresist layer to form a pattern in the photoresist layer.Type: ApplicationFiled: June 15, 2023Publication date: December 19, 2024Inventors: An-Ren ZI, Yen-Yu KUO, Ching-Yu CHANG, Chin-Hsiang LIN
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Publication number: 20240395855Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, first and second fin structures formed over the substrate, and an isolation structure between the first and second fin structures. The isolation structure can include a lower portion and an upper portion. The lower portion of the isolation structure can include a metal-free dielectric material. The upper portion of the isolation structure can include a metallic element and silicon.Type: ApplicationFiled: July 30, 2024Publication date: November 28, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pinyen LIN, Chin-Hsiang LIN, Huang-Lin CHAO
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Patent number: 12154822Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.Type: GrantFiled: April 18, 2023Date of Patent: November 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Hsiang Lin, Keng-Chu Lin, Shwang-Ming Jeng, Teng-Chun Tsai, Tsu-Hsiu Perng, Fu-Ting Yen
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Publication number: 20240387247Abstract: In accordance with an aspect of the present disclosure, in a pattern forming method for a semiconductor device, a first opening is formed in an underlying layer disposed over a substrate. The first opening is expanded in a first axis by directional etching to form a first groove in the underlying layer. A resist pattern is formed over the underlying layer. The resist pattern includes a second opening only partially overlapping the first groove. The underlying layer is patterned by using the resist pattern as an etching mask to form a second groove.Type: ApplicationFiled: July 29, 2024Publication date: November 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Gun LIU, Chin-Hsiang LIN, Chih-Ming LAI, Wei-Liang LIN, Yung-Sung YEN
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Publication number: 20240387240Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.Type: ApplicationFiled: July 26, 2024Publication date: November 21, 2024Inventors: Chin-Hsiang Lin, Keng-Chu Lin, Shwang-Ming Jeng, Teng-Chun Tsai, Tsu-Hsiu Perng, Fu-Ting Yen
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Patent number: 12148653Abstract: In accordance with an aspect of the present disclosure, in a pattern forming method for a semiconductor device, a first opening is formed in an underlying layer disposed over a substrate. The first opening is expanded in a first axis by directional etching to form a first groove in the underlying layer. A resist pattern is formed over the underlying layer. The resist pattern includes a second opening only partially overlapping the first groove. The underlying layer is patterned by using the resist pattern as an etching mask to form a second groove.Type: GrantFiled: May 10, 2021Date of Patent: November 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ru-Gun Liu, Chin-Hsiang Lin, Chih-Ming Lai, Wei-Liang Lin, Yung-Sung Yen
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Publication number: 20240377739Abstract: A method for manufacturing a semiconductor device includes forming a photoresist layer including a photoresist composition over a substrate. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a patterned photoresist. The photoresist composition includes a photoactive compound and a resin comprising a radical-active functional group and an acid labile group.Type: ApplicationFiled: July 24, 2024Publication date: November 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Siao-Shan WANG, Ching-Yu CHANG, Chin-Hsiang LIN
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Publication number: 20240377731Abstract: The present disclosure provides a method for lithography patterning in accordance with some embodiments. The method includes forming a photoresist layer over a substrate, wherein the photoresist layer includes a metal-containing chemical; performing an exposing process to the photoresist layer; and performing a first developing process to the photoresist layer using a first developer, thereby forming a patterned resist layer, wherein the first developer includes a first solvent and a chemical additive to remove metal residuals generated from the metal-containing chemical.Type: ApplicationFiled: July 22, 2024Publication date: November 14, 2024Inventors: An-Ren Zi, Joy Cheng, Ching-Yu Chang, Chin-Hsiang Lin
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Patent number: 12135502Abstract: A method for manufacturing a semiconductor device includes forming a photoresist layer including a photoresist composition over a substrate. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a patterned photoresist. The photoresist composition includes a photoactive compound and a resin comprising a radical-active functional group and an acid labile group.Type: GrantFiled: August 8, 2023Date of Patent: November 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Siao-Shan Wang, Ching-Yu Chang, Chin-Hsiang Lin
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Publication number: 20240363726Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.Type: ApplicationFiled: July 8, 2024Publication date: October 31, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Hsiang Lin, Teng-Chun TSAI, Huang-Lin Chao, Akira Mineji
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Publication number: 20240345472Abstract: A method for preparing a pellicle assembly includes reducing the thickness of one or more initial membrane(s) to obtain a pellicle membrane. The pellicle membrane is then affixed to a mounting frame to obtain the pellicle assembly. Compressive pressure can be applied to reduce the thickness of the initial membrane(s). Alternatively, the thickness can be reduced by stretching the initial membrane(s) to obtain an extended membrane. A mounting frame is then affixed to a portion of the extended membrane. The mounting frame and the portion of the extended membrane are then separated from the remainder of the extended membrane to obtain the pellicle assembly. The resulting pellicle assemblies include a pellicle membrane that is attached to a mounting frame. The pellicle membrane can be formed from nanotubes and has a combination of high transmittance, low deflection, and small pore size.Type: ApplicationFiled: June 24, 2024Publication date: October 17, 2024Inventors: Hsin-Chang Lee, Pei-Cheng Hsu, Ta-Cheng Lien, Li-Jui Chen, Tsai-Sheng Gau, Chin-Hsiang Lin
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Publication number: 20240345471Abstract: A pellicle for an EUV photo mask includes a membrane attached to a frame. The membrane includes nanotubes, Ru—O—X catalyst structures partially covering a surface of each nanotube, and a protection layer to cover the Ru—O—X catalyst structures and the surface of each nanotube. X is a metal element of Mo, Ti, Zr or Nb. The Ru—O—X catalyst structures include first nano-particles of a X-containing material formed on the surface of each nanotube, and second nano-particles of a Ru-containing material formed on the first nano-particles, thereby forming catalysts or catalyst bridges. The pellicle advantageously has high EUV light transmittance and improved endurance against attacking particles (such as hydrogen particles), thereby having prolonged lifetime.Type: ApplicationFiled: April 12, 2023Publication date: October 17, 2024Inventors: Pei-Cheng HSU, Hsin-Chang LEE, Huan-Ling LEE, Chin-Hsiang LIN
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Publication number: 20240329535Abstract: A method of forming semiconductor device includes depositing a coating layer over a substrate, forming a photoresist layer over the coating layer, exposing the photoresist layer to actinic radiation, and developing the photoresist layer to form a patterned photoresist layer. The coating layer includes a polymer containing a first unit having a pendant hydrogen donor group capable of producing a hydrogen radical upon exposure to the actinic radiation or heat, and a second unit having a pendant water donor group capable of producing water upon exposure to the actinic radiation or heat.Type: ApplicationFiled: July 28, 2023Publication date: October 3, 2024Inventors: Yen-Yu KUO, An-Ren ZI, Chen-Yu LIU, Ching-Yu CHANG, Chin-Hsiang LIN
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Patent number: 12106961Abstract: A method for forming a semiconductor device is provided. The method includes applying a photoresist composition over a substrate, thereby forming a photoresist layer over the substrate; performing a first baking process to the photoresist layer; exposing the photoresist layer to an extreme ultraviolet (EUV) radiation, thereby forming a pattern therein; performing a second baking process to the photoresist layer; and developing the photoresist layer having the pattern therein using a developer, thereby forming a patterned photoresist layer. The first baking process and the second baking process are conducted under an ambient atmosphere having a humidity level ranging from 55% to 100%.Type: GrantFiled: January 21, 2022Date of Patent: October 1, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: An-Ren Zi, Yahru Cheng, Ching-Yu Chang, Chin-Hsiang Lin