Patents by Inventor Chin-Hsiang Lin

Chin-Hsiang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210103218
    Abstract: A method is provided including forming a first layer over a substrate and forming an adhesion layer over the first layer. The adhesion layer has a composition including an epoxy group. A photoresist layer is formed directly on the adhesion layer. A portion of the photoresist layer is exposed to a radiation source. The composition of the adhesion layer and the exposed portion of the photoresist layer cross-link using the epoxy group. Thee photoresist layer is then developed (e.g., by a negative tone developer) to form a photoresist pattern feature, which may overlie the formed cross-linked region.
    Type: Application
    Filed: December 7, 2020
    Publication date: April 8, 2021
    Inventors: Chen-Yu LIU, Tzu-Yang LIN, Ya-Ching CHANG, Ching-Yu CHANG, Chin-Hsiang LIN
  • Publication number: 20210103213
    Abstract: The present disclosure provides a method for lithography patterning in accordance with some embodiments. The method includes forming a photoresist layer over a substrate, wherein the photoresist layer includes a metal-containing chemical; performing an exposing process to the photoresist layer; and performing a first developing process to the photoresist layer using a first developer, thereby forming a patterned resist layer, wherein the first developer includes a first solvent and a chemical additive to remove metal residuals generated from the metal-containing chemical.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 8, 2021
    Inventors: An-Ren Zi, Joy Cheng, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10971296
    Abstract: A device includes a substrate, and a vertical inductor over the substrate. The vertical inductor includes a plurality of parts formed of metal, wherein each of the parts extends in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect neighboring ones of the plurality of parts of the vertical inductor.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tsung Yen, Huan-Neng Chen, Yu-Ling Lin, Chin-Wei Kuo, Mei-Show Chen, Ho-Hsiang Chen, Min-Chie Jeng
  • Patent number: 10971397
    Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate is provided. The substrate includes a pixel region having a first conductive region and a logic region having a second conductive region. A dielectric layer is formed on the substrate to cover the first conductive region. A first contact opening is formed in the dielectric layer to expose the first conductive region. A doped polysilicon layer is sequentially formed in the first contact opening. A first metal silicide layer is formed on the doped polysilicon layer. A second contact opening is formed in the dielectric layer to expose the second conductive region. A barrier layer and a metal layer are respectively formed in the first contact opening and the second contact opening.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: April 6, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chia-Jung Hsu, Chun-Ya Chiu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20210096475
    Abstract: A method of manufacturing a semiconductor device includes dividing a number of dies along an x axis in a die matrix in each exposure field in an exposure field matrix delineated on the semiconductor substrate, wherein the x axis is parallel to one edge of a smallest rectangle enclosing the exposure field matrix. A number of dies is divided along a y axis in the die matrix, wherein the y axis is perpendicular to the x axis. Sequences SNx0, SNx1, SNx, SNxr, SNy0, SNy1, SNy, and SNyr are formed. p*(Nbx+1)?2 stepping operations are performed in a third direction and first sequence exposure/stepping/exposure operations and second sequence exposure/stepping/exposure operations are performed alternately between any two adjacent stepping operations as well as before a first stepping operation and after a last stepping operation. A distance of each stepping operation in order follows the sequence SNx.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Inventors: Shinn-Sheng YU, Ru-Gun LIU, Hsu-Ting HUANG, Kenji YAMAZOE, Minfeng CHEN, Shuo-Yen CHOU, Chin-Hsiang LIN
  • Patent number: 10965840
    Abstract: A display and a color correction method are disclosed. The display includes a panel and a backlight module. The color correction method includes steps of: (a) sensing a real-time backlight intensity of the backlight module; (b) increasing a backlight intensity of the backlight module when the real-time backlight intensity is different from a standard backlight intensity of the backlight module; (c) sensing a compensated backlight intensity of the backlight module and estimating a first real-time color information of the panel according to the compensated backlight intensity and a first panel color characteristic information, wherein the first panel color characteristic information corresponds to the penetration characteristics of the panel; and (d) estimating a first color gain compensation value for the panel according to the first real-time color information and compensating the colors displayed on the panel when the panel displaying an image according to the first color gain compensation value.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: March 30, 2021
    Assignee: Qisda Corporation
    Inventors: Chun-Hsiang Liao, Chin-Sheng Lin
  • Publication number: 20210082960
    Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.
    Type: Application
    Filed: November 24, 2020
    Publication date: March 18, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao, Sheng-Hsiung Chen, Chin-Chou Liu
  • Publication number: 20210074538
    Abstract: A method of manufacturing a semiconductor device includes forming a first protective layer over an edge portion of a first main surface of a semiconductor substrate. A metal-containing photoresist layer is formed over the first main surface of the semiconductor substrate. The first protective layer is removed, and the metal-containing photoresist layer is selectively exposed to actinic radiation. A second protective layer is formed over the edge portion of the first main surface of the semiconductor substrate. The selectively exposed photoresist layer is developed to form a patterned photoresist layer, and the second protective layer is removed.
    Type: Application
    Filed: August 12, 2020
    Publication date: March 11, 2021
    Inventors: An-Ren ZI, Ching-Yu CHANG, Chin-Hsiang LIN
  • Publication number: 20210069272
    Abstract: Provided is a method for skin whitening, ultraviolet radiation protection, and anti-glycation by using a green mango extract. Also provided is a method for anti-glycation by using compounds of hydrolyzable tannins isolated from the green mango extract.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 11, 2021
    Inventors: Yung-Hsiang Lin, Chin-Hsiu Yu, Yu-Ming Chung
  • Patent number: 10940174
    Abstract: Provided is a method for skin whitening, ultraviolet radiation protection, and anti-glycation by using a green mango extract. Also provided is a method for anti-glycation by using compounds of hydrolyzable tannins isolated from the green mango extract.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: March 9, 2021
    Assignee: TCI CO., LTD.
    Inventors: Yung-Hsiang Lin, Chin-Hsiu Yu, Yu-Ming Chung
  • Publication number: 20210063888
    Abstract: A method of forming a patterned photoresist layer includes the following operations: (i) forming a patterned photoresist on a substrate; (ii) forming a molding layer covering the patterned photoresist; (iii) reflowing the patterned photoresist in the molding layer; and (iv) removing the molding layer from the reflowed patterned photoresist. In some embodiments, the molding layer has a glass transition temperature that is greater than or equal to the glass transition temperature of the patterned photoresist. In yet some embodiments, the molding layer has a glass transition temperature that is 3° C.-30° C. less than the glass transition temperature of the patterned photoresist.
    Type: Application
    Filed: May 27, 2020
    Publication date: March 4, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chih HO, Ching-Yu CHANG, Chin-Hsiang LIN
  • Publication number: 20210057543
    Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer haying a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Hsiang LIN, Teng-Chun TSAI, Akira MINEJI, Huang-Lin CHAO
  • Publication number: 20210050255
    Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate is provided. The substrate includes a pixel region having a first conductive region and a logic region having a second conductive region. A dielectric layer is formed on the substrate to cover the first conductive region. A first contact opening is formed in the dielectric layer to expose the first conductive region. A doped polysilicon layer is sequentially formed in the first contact opening. A first metal silicide layer is formed on the doped polysilicon layer. A second contact opening is formed in the dielectric layer to expose the second conductive region. A barrier layer and a metal layer are respectively formed in the first contact opening and the second contact opening.
    Type: Application
    Filed: September 12, 2019
    Publication date: February 18, 2021
    Applicant: United Microelectronics Corp.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chia-Jung Hsu, Chun-Ya Chiu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20210050456
    Abstract: A manufacturing method of a semiconductor device includes the following steps. An opening is formed penetrating a dielectric layer on a semiconductor substrate. A stacked structure is formed on the dielectric layer. The stacked structure includes a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer, a sacrificial layer formed on the first semiconductor layer, and a second semiconductor layer formed on the sacrificial layer. A patterning process is performed for forming a fin-shaped structure including the first semiconductor layer, the sacrificial layer, and the second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin-shaped structure. The first semiconductor layer in the fin-shaped structure is etched to become a first semiconductor wire by the etching process. The second semiconductor layer in the fin-shaped structure is etched to become a second semiconductor wire by the etching process.
    Type: Application
    Filed: September 16, 2019
    Publication date: February 18, 2021
    Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chun-Ya Chiu, Chia-Jung Hsu, Yu-Hsiang Lin
  • Patent number: 10918683
    Abstract: Provided is a method for reducing fat accumulation in and oxidative damage to liver cells by using a green mango extract. Also provided is a method for reducing fat accumulation in liver cells by using compounds of hydrolyzable tannins isolated from the green mango extract.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: February 16, 2021
    Assignee: TCI CO., LTD.
    Inventors: Yung-Hsiang Lin, Chin-Hsiu Yu, Shan-Yu Lin
  • Patent number: 10905674
    Abstract: A method for at least one of increasing the synthesis of melatonin and promoting the secretion of melatonin is provided, wherein the method comprises administering to a subject in need an effective amount of a compound of formula (I): A method for at least one of treating diseases related to neurometabolic disorder, preventing diseases related to neurometabolic disorder, regulating appetite, regulating mood, regulating vasoconstriction, regulating hemostatic function and regulating immune response is also provided, wherein the method comprises administering to a subject in need an effective amount of a compound of formula (I) as described above.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: February 2, 2021
    Assignee: TCI CO., LTD.
    Inventors: Yung-Hsiang Lin, Chin-Hsiu Yu, Yu-Hung Su, Shan-Yu Lin, Yu-Ming Chung
  • Patent number: 10903239
    Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: January 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao, Sheng-Hsiung Chen, Chin-Chou Liu
  • Publication number: 20210010137
    Abstract: A control system for a plasma treatment apparatus includes a wafer treatment device. The wafer treatment device includes a vapor chamber and an upper electrode assembly. The upper electrode assembly includes a gas distribution plate having a plurality of holes. The upper electrode assembly includes an upper electrode having at least one gas nozzle and at least one controllable valve connected to the at least one gas nozzle for controlling a flow of gas from a gas supply to the holes via the at least one gas nozzle. The at least one gas nozzle is separated from the gate distribution plate by a gap. The control system includes a measurement device configured to measure a thickness profile of a wafer. The control system includes a controller configured to generate a control signal. The at least one controllable valve is configured to be adjusted based on the control signal.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventors: Yen-Shuo SU, Ying XIAO, Chin-Hsiang LIN
  • Publication number: 20210013048
    Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventors: Ru-Gun LIU, Chih-Ming LAI, Wei-Liang LIN, Yung-Sung YEN, Ken-Hsien HSIEH, Chin-Hsiang LIN
  • Publication number: 20210004694
    Abstract: An IoT system includes a computing module for controlling an integral function of the system and including an analysis unit and a machine learning unit. The analysis unit is capable of operational analysis and creating a predictive model and creating a predictive model according to the data analyzed. The machine learning unit has an algorithm function to create a corresponding learning model. An IoT module is electrically connected to the computing module to serve as an intermediate role. At least one detection unit is electrically connected to the IoT module and disposed in soil to detect data of environmental and soil conditions and sends the data detected to the computing module for subsequent analysis.
    Type: Application
    Filed: October 20, 2019
    Publication date: January 7, 2021
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Wen-Liang Chen, Lung-Chieh Chen, Szu-Chia Chen, Wei-Han Chen, Chun-Yu Chu, Yu-Chi Shih, Yu-Ci Chang, Tzu-I Hsieh, Yen-Ling Chen, Li-Chi Peng, Meng-Zhan Lee, Jui-Yu Ho, Chi-Yao Ku, Nian-Ruei Deng, Yuan-Yao Chan, Erick Wang, Tai-Hsiang Yen, Shao-Yu Chiu, Jiun-Yi Lin, Yun-Wei Lin, Fung Ling Ng, Yi-Bing Lin, Chin-Cheng Wang