Patents by Inventor Chin-Hsiang Lin

Chin-Hsiang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11581217
    Abstract: A method for forming openings in an underlayer includes: forming a photoresist layer on an underlayer formed on a substrate; exposing the photoresist layer; forming photoresist patterns by developing the exposed photoresist layer, the photoresist patterns covering regions of the underlayer in which the openings are to be formed; forming a liquid layer over the photoresist patterns; after forming the liquid layer, performing a baking process so as to convert the liquid layer to an organic layer in a solid form; performing an etching back process to remove a portion of the organic layer on a level above the photoresist patterns; removing the photoresist patterns, so as to expose portions of the underlayer by the remaining portion of the organic layer; forming the openings in the underlayer by using the remaining portion of the organic layer as an etching mask; and removing the remaining portion of the organic layer.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: February 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Yang Lin, Cheng-Han Wu, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 11569090
    Abstract: A method of depositing a material on one of two, but not both, sidewalls of a raised structure formed on a substrate includes tilting a normal of the substrate away from a source of the deposition material or tilting the source of the deposition material away from the normal of the substrate. The method may be implemented by a plasma-enhanced chemical vapor deposition (PECVD) technique.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Chun Huang, Ya-Wen Yeh, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Ru-Gun Liu, Chin-Hsiang Lin, Yu-Tien Shen
  • Publication number: 20230028673
    Abstract: A photoresist composition includes a conjugated resist additive, a photoactive compound, and a polymer resin. The conjugated resist additive is one or more selected from the group consisting of a polyacetylene, a polythiophene, a polyphenylenevinylene, a polyfluorene, a polypryrrole, a polyphenylene, and a polyaniline. The polyacetylene, polythiophene, polyphenylenevinylene, polyfluorene, polypryrrole, the polyphenylene, and polyaniline includes a substituent selected from the group consisting of an alkyl group, an ether group, an ester group, an alkene group, an aromatic group, an anthracene group, an alcohol group, an amine group, a carboxylic acid group, and an amide group. Another photoresist composition includes a polymer resin having a conjugated moiety and a photoactive compound. The conjugated moiety is one or more selected from the group consisting of a polyacetylene, a polythiophene, a polyphenylenevinylene, a polyfluorene, a polypryrrole, a polyphenylene, and a polyaniline.
    Type: Application
    Filed: July 25, 2022
    Publication date: January 26, 2023
    Inventors: Chun-Chih HO, Ching-Yu CHANG, Chin-Hsiang LIN
  • Publication number: 20230012705
    Abstract: A method for forming a semiconductor device is provided. The method includes applying a photoresist composition over a substrate, thereby forming a photoresist layer over the substrate; performing a first baking process to the photoresist layer; exposing the photoresist layer to an extreme ultraviolet (EUV) radiation, thereby forming a pattern therein; performing a second baking process to the photoresist layer; and developing the photoresist layer having the pattern therein using a developer, thereby forming a patterned photoresist layer. The first baking process and the second baking process are conducted under an ambient atmosphere having a humidity level ranging from 55% to 100%.
    Type: Application
    Filed: January 21, 2022
    Publication date: January 19, 2023
    Inventors: An-Ren ZI, Yahru CHENG, Ching-Yu CHANG, Chin-Hsiang LIN
  • Publication number: 20220413378
    Abstract: Methods for removing a catalyst particle from a nanotube film used in a photolithographic patterning process are disclosed. The catalyst particle is identified based on its size in the nanotube film. This identification can be done using an inspection device such as a confocal microscope, which permits comparison of images taken in two or more separate focal planes to determine the size of particles. The catalyst particle is then exposed to a first absorption wavelength using a laser, which is selectively absorbed by the catalyst particle and which heats the catalyst particle to remove the catalyst particle from the nanotube film. Optionally, the catalyst particle-free nanotube film can be further exposed to a second absorption wavelength which is selectively absorbed by the film and promotes repair of the film. The resulting nanotube film can be used in a pellicle membrane.
    Type: Application
    Filed: April 18, 2022
    Publication date: December 29, 2022
    Inventors: Ping-Hsun Lin, Pei-Cheng Hsu, Huan-Ling Lee, Ta-Cheng Lien, Hsin-Chang Lee, Chin-Hsiang Lin
  • Publication number: 20220392763
    Abstract: A method of manufacturing a semiconductor device includes forming a first protective layer over an edge portion of a first main surface of a semiconductor substrate. A metal-containing photoresist layer is formed over the first main surface of the semiconductor substrate. The first protective layer is removed, and the metal-containing photoresist layer is selectively exposed to actinic radiation. A second protective layer is formed over the edge portion of the first main surface of the semiconductor substrate. The selectively exposed photoresist layer is developed to form a patterned photoresist layer, and the second protective layer is removed.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 8, 2022
    Inventors: An-Ren ZI, Ching-Yu CHANG, Chin-Hsiang LIN
  • Publication number: 20220382156
    Abstract: A method includes forming a photoresist layer over a substrate, wherein the photoresist layer includes a polymer, a sensitizer, and a photo-acid generator (PAG), wherein the sensitizer includes a resonance ring that includes nitrogen and at least one double bond. The method further includes performing an exposing process to the photoresist layer. The method further includes developing the photoresist layer, thereby forming a patterned photoresist layer.
    Type: Application
    Filed: July 29, 2022
    Publication date: December 1, 2022
    Inventors: Wei-Han Lai, Chin-Hsiang Lin, Chien-Wei Wang
  • Publication number: 20220365421
    Abstract: A method for preparing a pellicle assembly includes reducing the thickness of one or more initial membrane(s) to obtain a pellicle membrane. The pellicle membrane is then affixed to a mounting frame to obtain the pellicle assembly. Compressive pressure can be applied to reduce the thickness of the initial membrane(s). Alternatively, the thickness can be reduced by stretching the initial membrane(s) to obtain an extended membrane. A mounting frame is then affixed to a portion of the extended membrane. The mounting frame and the portion of the extended membrane are then separated from the remainder of the extended membrane to obtain the pellicle assembly. The resulting pellicle assemblies include a pellicle membrane that is attached to a mounting frame. The pellicle membrane can be formed from nanotubes and has a combination of high transmittance, low deflection, and small pore size.
    Type: Application
    Filed: May 12, 2021
    Publication date: November 17, 2022
    Inventors: Hsin-Chang Lee, Pei-Cheng Hsu, Ta-Cheng Lien, Li-Jui Chen, Tsai-Sheng Gau, Chin-Hsiang Lin
  • Publication number: 20220365438
    Abstract: An extreme ultraviolet lithography (EUVL) method includes providing at least two phase-shifting mask areas having a same pattern. A resist layer is formed over a substrate. An optimum exposure dose of the resist layer is determined, and a latent image is formed on a same area of the resist layer by a multiple exposure process. The multiple exposure process includes a plurality of exposure processes and each of the plurality of exposure processes uses a different phase-shifting mask area from the at least two phase-shifting mask areas having a same pattern.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Inventors: Shinn-Sheng YU, Ru-Gun LIU, Hsu-Ting HUANG, Chin-Hsiang LIN
  • Publication number: 20220365420
    Abstract: A pellicle assembly includes a pellicle membrane and a conformal coating on an outer surface of the pellicle membrane. The pellicle membrane can be formed with multiple layers and has a combination of high transmittance, low deflection, and small pore size. The conformal coating is intended to protect the pellicle membrane from damage that can occur due to heat and hydrogen plasma created during EUV exposure.
    Type: Application
    Filed: May 12, 2021
    Publication date: November 17, 2022
    Inventors: Pei-Cheng Hsu, Ta-Cheng Lien, Hsin-Chang Lee, Tsai-Sheng Gau, Chin-Hsiang Lin
  • Publication number: 20220359756
    Abstract: An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Chin-Hsiang Lin, Tai-Chun Huang, Tien-I Bao
  • Patent number: 11495460
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a substrate, and forming a first layer over the material layer. The method also includes forming a second layer over the first layer, and the second layer includes an auxiliary. The method further includes forming a third layer over the second layer, and the third layer includes an inorganic material, the inorganic material includes a plurality of metallic cores, and a plurality of first linkers bonded to the metallic cores. A topmost surface of the second layer is in direct contact with a bottommost surface of the third layer. The method includes exposing a portion of the second layer by performing an exposure process, and the auxiliary reacts with the first linkers during the exposure process.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Ren Zi, Chin-Hsiang Lin, Ching-Yu Chang
  • Publication number: 20220334482
    Abstract: A patterning stack is provided. The patterning stack includes a bottom anti-reflective coating (BARC) layer over a substrate, a photoresist layer having a first etching resistance over the BARC layer, and a top coating layer having a second etching resistance greater than the first etching resistance over the photoresist layer. The top coating layer includes a polymer having a polymer backbone including at least one functional unit of high etching resistance and one or more acid labile groups attached to the polymer backbone or a silicon cage compound.
    Type: Application
    Filed: April 15, 2021
    Publication date: October 20, 2022
    Inventors: Tzu-Yang LIN, Ching-Yu CHANG, Chin-Hsiang LIN
  • Publication number: 20220308452
    Abstract: In a method, a resist material is dispensed through a tube of a nozzle of a resist pump system on a wafer. The tube extends from a top to a bottom of the nozzle and has upper, lower, and middle segments. When not dispensing, the resist material is retracted from the lower and the middle segments, and maintained in the upper segment of the tube. When retracting, a first solvent is flown through a tip of the nozzle at the bottom of the nozzle to fill the lower segment of the tube with the first solvent and to produce a gap in the middle segment of the tube between the resist material and the first solvent. The middle segment includes resist material residues on an inner surface wall of the tube and vapor of the first solvent. The vapor of the first solvent prevents the resist material residues from drying.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 29, 2022
    Inventors: Ya-Ching CHANG, Chen-Yu LIU, Ching-Yu CHANG, Chin-Hsiang LIN
  • Publication number: 20220285168
    Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 8, 2022
    Inventors: Ru-Gun LIU, Chih-Ming LAI, Wei-Liang LIN, Yung-Sung YEN, Ken-Hsien HSIEH, Chin-Hsiang LIN
  • Patent number: 11435817
    Abstract: A multi-power management system and an operation method for the multi-power management system are provided. The multi-power management system includes multiple adapters and a power supply circuit. The adapters respectively provide multiple powers. The power supply circuit receives multiple input power values of the adapters, and calculates multiple input power value contribution ratios of the adapters according to the input power values. The power supply circuit further provides a control signal according to a sum of the output current values of multiple output current values of the powers and the input power value contribution ratios. The adapters adjust the output current values and multiple output voltage values respectively in response to the control signal.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: September 6, 2022
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Chin-Hsiang Lin, Chien-Lee Liu, Tzu-Chiang Mi, Yi-Hsun Lin
  • Patent number: 11437161
    Abstract: An apparatus includes an extreme ultraviolet light source vessel having an intermediate focus, a scanner having a light source aperture, and a deflection module arranged between the intermediate focus and the light source aperture. The deflection module includes a first electrode plate and a second electrode plate, configured to create an electric field therebetween. Tin particles moving from the intermediate focus to the light source aperture passes through the deflection module, and are deflected by the electric field therein.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Lin Chang, Chieh Hsieh, Shang-Chieh Chien, Han-Lung Chang, Heng-Hsin Liu, Li-Jui Chen, Chin-Hsiang Lin
  • Patent number: 11429027
    Abstract: An extreme ultraviolet lithography (EUVL) method includes providing at least two phase-shifting mask areas having a same pattern. A resist layer is formed over a substrate. An optimum exposure dose of the resist layer is determined, and a latent image is formed on a same area of the resist layer by a multiple exposure process. The multiple exposure process includes a plurality of exposure processes and each of the plurality of exposure processes uses a different phase-shifting mask area from the at least two phase-shifting mask areas having a same pattern.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shinn-Sheng Yu, Ru-Gun Liu, Hsu-Ting Huang, Chin-Hsiang Lin
  • Patent number: 11422465
    Abstract: A method includes forming a photoresist layer over a substrate, wherein the photoresist layer includes a polymer, a sensitizer, and a photo-acid generator (PAG), wherein the sensitizer includes a resonance ring that includes nitrogen and at least one double bond. The method further includes performing an exposing process to the photoresist layer. The method further includes developing the photoresist layer, thereby forming a patterned photoresist layer.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Han Lai, Chin-Hsiang Lin, Chien-Wei Wang
  • Publication number: 20220260931
    Abstract: A method of manufacturing a semiconductor device includes dividing a number of dies along an x axis in a die matrix in each exposure field in an exposure field matrix delineated on the semiconductor substrate, wherein the x axis is parallel to one edge of a smallest rectangle enclosing the exposure field matrix. A number of dies is divided along a y axis in the die matrix, wherein the y axis is perpendicular to the x axis. Sequences SNx0, SNx1, SNx, SNxr, SNy0, SNy1, SNy, and SNyr are formed. p*(Nbx+1)?2 stepping operations are performed in a third direction and first sequence exposure/stepping/exposure operations and second sequence exposure/stepping/exposure operations are performed alternately between any two adjacent stepping operations as well as before a first stepping operation and after a last stepping operation. A distance of each stepping operation in order follows the sequence SNx.
    Type: Application
    Filed: April 29, 2022
    Publication date: August 18, 2022
    Inventors: Shinn-Sheng YU, Ru-Gun LIU, Hsu-Ting HUANG, Kenji YAMAZOE, Minfeng CHEN, Shuo-Yen CHOU, Chin-Hsiang LIN