Patents by Inventor Chin-Hsiang Lin

Chin-Hsiang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230245900
    Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.
    Type: Application
    Filed: April 10, 2023
    Publication date: August 3, 2023
    Inventors: Yen-Hao Chen, Wei-Han Lai, Ching-Yu Chang, Chin-Hsiang Lin
  • Publication number: 20230245889
    Abstract: A method of manufacturing a semiconductor device includes forming a first protective layer over an edge portion of a first main surface of a semiconductor substrate. A metal-containing photoresist layer is formed over the first main surface of the semiconductor substrate. The first protective layer is removed, and the metal-containing photoresist layer is selectively exposed to actinic radiation. A second protective layer is formed over the edge portion of the first main surface of the semiconductor substrate. The selectively exposed photoresist layer is developed to form a patterned photoresist layer, and the second protective layer is removed.
    Type: Application
    Filed: April 10, 2023
    Publication date: August 3, 2023
    Inventors: An-Ren ZI, Ching-Yu CHANG, Chin-Hsiang LIN
  • Publication number: 20230238275
    Abstract: A method of forming a semiconductor device includes forming a plurality of non-insulator structures on a substrate, the plurality of non-insulator structures being spaced apart by trenches, forming a sacrificial layer overfilling the trenches, reflowing the sacrificial layer at an elevated temperature, wherein a top surface of the sacrificial layer after the reflowing is lower than a top surface of the sacrificial layer before the reflowing, etching back the sacrificial layer to lower the top surface of the sacrificial layer to fall below top surfaces of the plurality of non-insulator structures, forming a dielectric layer on the sacrificial layer, and removing the sacrificial layer to form air gaps below the dielectric layer.
    Type: Application
    Filed: April 14, 2022
    Publication date: July 27, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chih HO, Yu-Chung SU, Ching-Yu CHANG, Chin-Hsiang LIN
  • Publication number: 20230236496
    Abstract: A method for forming a pellicle for an extreme ultraviolet lithography is provided. The method includes forming a pellicle membrane over a filter membrane and transferring the pellicle membrane from the filter membrane to a membrane border. Forming the pellicle membrane includes growing carbon nanotubes (CNTs) from in-situ formed metal catalyst particles in a first reaction zone of a reactor, each of the CNTs including a metal catalyst particle at a growing tip thereof, growing boron nitride nanotubes (BNNTs) to surround individual CNTs in a second reaction zone of the reactor downstream of the first reaction zone, thereby forming heterostructure nanotubes each including a CNT core and a BNNT shell, and collecting the heterostructure nanotubes on the filter membrane. The metal catalyst particles are partially or completely removed during growing the BNNTs.
    Type: Application
    Filed: May 20, 2022
    Publication date: July 27, 2023
    Inventors: Pei-Cheng HSU, Huan-Ling LEE, Hsin-Chang LEE, Chin-Hsiang LIN
  • Patent number: 11709435
    Abstract: A method of manufacturing a semiconductor device includes dividing a number of dies along an x axis in a die matrix in each exposure field in an exposure field matrix delineated on the semiconductor substrate, wherein the x axis is parallel to one edge of a smallest rectangle enclosing the exposure field matrix. A number of dies is divided along a y axis in the die matrix, wherein the y axis is perpendicular to the x axis. Sequences SNx0, SNx1, SNx, SNxr, SNy0, SNy1, SNy, and SNyr are formed. p*(Nbx+1)?2 stepping operations are performed in a third direction and first sequence exposure/stepping/exposure operations and second sequence exposure/stepping/exposure operations are performed alternately between any two adjacent stepping operations as well as before a first stepping operation and after a last stepping operation. A distance of each stepping operation in order follows the sequence SNx.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: July 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shinn-Sheng Yu, Ru-Gun Liu, Hsu-Ting Huang, Kenji Yamazoe, Minfeng Chen, Shuo-Yen Chou, Chin-Hsiang Lin
  • Patent number: 11703765
    Abstract: A photoresist composition includes a photoactive compound and a polymer. The polymer has a polymer backbone including one or more groups selected from: The polymer backbone includes at least one group selected from B, C-1, or C-2, wherein ALG is an acid labile group, and X is linking group.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: July 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzu-Yang Lin, Ching-Yu Chang, Chin-Hsiang Lin
  • Publication number: 20230170218
    Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.
    Type: Application
    Filed: January 30, 2023
    Publication date: June 1, 2023
    Inventors: Shih-Chun Huang, Ya-Wen Yeh, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Ru-Gun Liu, Chin-Hsiang Lin, Yu-Tien Shen
  • Patent number: 11664268
    Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Hsiang Lin, Keng-Chu Lin, Shwang-Ming Jeng, Teng-Chun Tsai, Tsu-Hsiu Perng, Fu-Ting Yen
  • Publication number: 20230161261
    Abstract: Coated nanotubes and bundles of nanotubes are formed into membranes useful in optical assemblies in EUV photolithography systems. These optical assemblies are useful in methods for patterning materials on a semiconductor substrate. Such methods involve generating, in a UV lithography system, UV radiation. The UV radiation is passed through a coating layer of the optical assembly, e.g., a pellicle assembly. The UV radiation that has passed through the coating layer is passed through a matrix of individual nanotubes or matrix of nanotube bundles. UV radiation that passes through the matrix of individual nanotubes or matrix of nanotube bundles is reflected from a mask and received at a semiconductor substrate.
    Type: Application
    Filed: May 16, 2022
    Publication date: May 25, 2023
    Inventors: Wei-Hao LEE, Pei-Cheng HSU, Huan-Ling LEE, Ta-Cheng LIEN, Hsin-Chang LEE, Chin-Hsiang LIN
  • Patent number: 11656553
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a substrate and forming a resist layer over the material layer. The method includes exposing a portion of the resist layer. The resist layer includes a photoacid generator (PAG) group, a quencher group, an acid-labile group (ALG) and a polar unit (PU). The method also includes performing a baking process on the resist layer and developing the resist layer to form a patterned resist layer. The method further includes doping a portion of the material layer by using the patterned resist layer as a mask to form a doped region. In addition, the method includes removing the patterned resist layer.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: May 23, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Yen Lin, Ching-Yu Chang, Chin-Hsiang Lin
  • Publication number: 20230135538
    Abstract: A pellicle assembly includes a pellicle membrane with a nanotube layer formed from nanotubes having a minimum length of 1,000 ?m. The pellicle membrane can be formed with multiple layers and has a combination of high transmittance, low deflection, and small pore size. A conformal coating may applied to an outer surface of the pellicle membrane. The conformal coating is intended to protect the pellicle membrane from damage that can occur due to heat and hydrogen plasma created during EUV exposure.
    Type: Application
    Filed: February 28, 2022
    Publication date: May 4, 2023
    Inventors: Pei-Cheng Hsu, Ping-Huan Tsai, Huan-Ling Lee, Ta-Cheng Lien, Hsin-Chang Lee, Chin-Hsiang Lin
  • Patent number: 11626285
    Abstract: A method of manufacturing a semiconductor device includes forming a first protective layer over an edge portion of a first main surface of a semiconductor substrate. A metal-containing photoresist layer is formed over the first main surface of the semiconductor substrate. The first protective layer is removed, and the metal-containing photoresist layer is selectively exposed to actinic radiation. A second protective layer is formed over the edge portion of the first main surface of the semiconductor substrate. The selectively exposed photoresist layer is developed to form a patterned photoresist layer, and the second protective layer is removed.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: April 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Ren Zi, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 11626293
    Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: April 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Hao Chen, Wei-Han Lai, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 11605538
    Abstract: A method includes forming protective layer over substrate edge and photoresist over substrate. Protective layer removed and photoresist exposed to radiation. Protective layer made of composition including acid generator and polymer having pendant acid-labile groups.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: March 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Ren Zi, Ching-Yu Chang, Chin-Hsiang Lin
  • Publication number: 20230065234
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, first and second fin structures formed over the substrate, and an isolation structure between the first and second fin structures. The isolation structure can include a lower portion and an upper portion. The lower portion of the isolation structure can include a metal-free dielectric material. The upper portion of the isolation structure can include a metallic element and silicon.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pinyen LIN, Chin-Hsiang LIN, Huang-Lin CHAO
  • Patent number: 11594528
    Abstract: A layout modification method for fabricating a semiconductor device is provided. The layout modification method includes calculating uniformity of critical dimensions of first and second portions in a patterned layer by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the first and second portions equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. The layout modification method further includes compensating non-uniformity of the first and second portions of the patterned layer according to the uniformity of critical dimensions to generate a modified layout. The first portion is divided into a plurality of first sub-portions. The second portion is divided into a plurality of second sub-portions. Each second sub-portion is surrounded by two of the first sub-portions.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Wen Cho, Fu-Jye Liang, Chun-Kuang Chen, Chih-Tsung Shih, Li-Jui Chen, Po-Chung Cheng, Chin-Hsiang Lin
  • Publication number: 20230056958
    Abstract: Novel photoresist developing compositions including a deprotonation agent, such as a nitrogen containing organic base capable of deprotonating a surface of portions of a photoresist layer exposed to radiation.
    Type: Application
    Filed: January 25, 2022
    Publication date: February 23, 2023
    Inventors: Tzu-Yang LIN, Chen-Yu LIU, Ching-Yu CHANG, Chin-Hsiang LIN
  • Patent number: 11581217
    Abstract: A method for forming openings in an underlayer includes: forming a photoresist layer on an underlayer formed on a substrate; exposing the photoresist layer; forming photoresist patterns by developing the exposed photoresist layer, the photoresist patterns covering regions of the underlayer in which the openings are to be formed; forming a liquid layer over the photoresist patterns; after forming the liquid layer, performing a baking process so as to convert the liquid layer to an organic layer in a solid form; performing an etching back process to remove a portion of the organic layer on a level above the photoresist patterns; removing the photoresist patterns, so as to expose portions of the underlayer by the remaining portion of the organic layer; forming the openings in the underlayer by using the remaining portion of the organic layer as an etching mask; and removing the remaining portion of the organic layer.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: February 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Yang Lin, Cheng-Han Wu, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 11569090
    Abstract: A method of depositing a material on one of two, but not both, sidewalls of a raised structure formed on a substrate includes tilting a normal of the substrate away from a source of the deposition material or tilting the source of the deposition material away from the normal of the substrate. The method may be implemented by a plasma-enhanced chemical vapor deposition (PECVD) technique.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Chun Huang, Ya-Wen Yeh, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Ru-Gun Liu, Chin-Hsiang Lin, Yu-Tien Shen
  • Publication number: 20230028673
    Abstract: A photoresist composition includes a conjugated resist additive, a photoactive compound, and a polymer resin. The conjugated resist additive is one or more selected from the group consisting of a polyacetylene, a polythiophene, a polyphenylenevinylene, a polyfluorene, a polypryrrole, a polyphenylene, and a polyaniline. The polyacetylene, polythiophene, polyphenylenevinylene, polyfluorene, polypryrrole, the polyphenylene, and polyaniline includes a substituent selected from the group consisting of an alkyl group, an ether group, an ester group, an alkene group, an aromatic group, an anthracene group, an alcohol group, an amine group, a carboxylic acid group, and an amide group. Another photoresist composition includes a polymer resin having a conjugated moiety and a photoactive compound. The conjugated moiety is one or more selected from the group consisting of a polyacetylene, a polythiophene, a polyphenylenevinylene, a polyfluorene, a polypryrrole, a polyphenylene, and a polyaniline.
    Type: Application
    Filed: July 25, 2022
    Publication date: January 26, 2023
    Inventors: Chun-Chih HO, Ching-Yu CHANG, Chin-Hsiang LIN