Abstract: A self-discharging circuit discharging electrical charges of an external energy storage device coupled to a power transmission line coupled between a power supply device and a load is provided. The self-discharging circuit includes a current-limiting unit, an internal energy storage unit, a voltage detection unit and a discharge unit. The current-limiting unit is coupled between the power transmission line and a first node. The internal energy storage unit is coupled between the first node and a ground node. The ground node receives a ground level. The voltage detection unit detects a level of the first node. The discharge unit is coupled between the power transmission line and a second node. When the level of the first node is less than a pre-determined level, the voltage detection unit directs the second node to couple to the ground node.

Abstract: A double patterning method comprises the following steps. First of all, a target layer and a mask layer stacked thereon are provided. Next, a first pattern opening is formed in the mask layer, and a width of the first pattern opening is measured to obtain a measuring value. Then, a second pattern opening is formed in the mask layer based on the measuring value, wherein the second pattern opening and the first pattern opening are co-planar. Finally, a bias trimming process is performed to trim the first pattern opening and the second pattern opening.

Abstract: An overlay mark applied to a LELE-type double patterning lithography (DPL) process including a first lithography step, a first etching step, a second lithography step and a second etching step in sequence is described. The overlay mark includes a first x-directional pattern and a first y-directional pattern of a previous layer, second x-directional and y-directional patterns of a current layer defined by the first lithography step, and third x-directional and y-directional patterns of the current layer defined by the second lithography step. The second x-directional patterns and the third x-directional patterns are arranged alternately beside the first x-directional pattern. The second y-directional patterns and the third y-directional patterns are arranged alternately beside the first y-directional pattern.

Abstract: An overlay mark applied to a LELE-type double patterning lithography (DPL) process including a first lithography step, a first etching step, a second lithography step and a second etching step in sequence is described. The overlay mark includes a first x-directional pattern and a first y-directional pattern of a previous layer, second x-directional and y-directional patterns of a current layer defined by the first lithography step, and third x-directional and y-directional patterns of the current layer defined by the second lithography step. The second x-directional patterns and the third x-directional patterns are arranged alternately beside the first x-directional pattern. The second y-directional patterns and the third y-directional patterns are arranged alternately beside the first y-directional pattern.

Abstract: An N work function metal for a gate stack of a field effect transistor (FinFET) and method of forming the same are provided. An embodiment FinFET includes a fin supported by a semiconductor substrate, the fin extending between a source and a drain and having a channel region, and a gate stack formed over the channel region of the fin, the gate stack including an N work function metal layer comprising an oxidation layer on opposing sides of a tantalum aluminide carbide (TaAlC) layer.

Abstract: A docking station including fixing base and at least one latching module is provided. The latching module includes a latching element, a first restoring element, a stopping element, a second restoring element and a pushing element. The first restoring element is connected to the latching element and the fixing base and drives the latching element to latch a tablet device. The stopping element is coupled to the latching element and has a recess. The second restoring element is connected to the stopping element and the fixing base and drives the stopping element to stop the latching element. The pushing element is adapted to be pushed and inserted into the recess to drive the stopping element to move away from the latching element, and the tablet device is adapted to be released from the latching element by pushing the latching element after the stopping element moves away from the latching element.

Abstract: The present invention provides a photo-mask for manufacturing structures on a semiconductor substrate, which comprises a photo-mask substrate, a first pattern, a second pattern and a forbidden pattern. A first active region, a second active region are defined on the photo-mask substrate, and a region other than the first active region and the second active region are defined as a forbidden region. The first pattern is disposed in the first active region and corresponds to a first structure on the semiconductor substrate. The second pattern is disposed in the second active region and corresponds to a second structure on the semiconductor substrate. The forbidden pattern is disposed in the forbidden region, wherein the forbidden pattern has a dimension beyond resolution capability of photolithography and is not used to form any corresponding structure on the semiconductor substrate. The present invention further provides a method of manufacturing semiconductor structures.

Abstract: An asymmetry compensation method used in a lithography overlay process and including steps of: providing a first substrate, wherein a circuit layout is disposed on the first substrate, a first mask layer and a second mask layer together having an x-axis allowable deviation range and an y-axis allowable deviation range relative to the circuit layout are stacked sequentially on the circuit layout, wherein the x-axis allowable deviation range is unequal to the y-axis allowable deviation range; and calculating an x-axis final compensation parameter and an y-axis final compensation parameter base on the unequal x-axis allowable deviation range and the y-axis allowable deviation range.

Abstract: A docking station including fixing base and at least one latching module is provided. The latching module includes a latching element, a first restoring element, a stopping element, a second restoring element and a pushing element. The first restoring element is connected to the latching element and the fixing base and drives the latching element to latch a tablet device. The stopping element is coupled to the latching element and has a recess. The second restoring element is connected to the stopping element and the fixing base and drives the stopping element to stop the latching element. The pushing element is adapted to be pushed and inserted into the recess to drive the stopping element to move away from the latching element, and the tablet device is adapted to be released from the latching element by pushing the latching element after the stopping element moves away from the latching element.

Abstract: A method of correcting an overlay error includes the following steps. First, an overlay mark disposed on a substrate is captured so as to generate overlay mark information. The overlay mark includes at least a pair of first mark patterns and at least a second mark pattern above the first mark patterns. Then, the overlay mark information is calculated to generate an offset value between two first mark patterns and to generate a shift value between the second mark pattern and one of the first mark patterns. Finally, the offset value is used to compensate the shift value so as to generate an amended shift value.

Abstract: A management method of a hybrid storage unit and an electronic apparatus of the hybrid storage unit are provided. The electronic apparatus includes a hybrid storage unit. The hybrid storage unit includes a first storage unit and a second storage unit. The second storage unit includes a first storage area and a second storage area. If a relationship between the electronic apparatus and an external apparatus is detected as being an undocked relationship, the first storage unit is disabled by a controller of the hybrid storage unit, and the second storage area serves to simulate and replace the first storage unit. The controller reports a storage unit status change notification to an operating system, so as to allow the operating system to re-enumerate the hybrid storage unit.

Abstract: A device includes a substrate, a semiconductor fin over the substrate, and a gate dielectric layer on a top surface and sidewalls of the semiconductor fin. A gate electrode is spaced apart from the semiconductor fin by the gate dielectric layer. The gate electrode includes a top portion over and aligned to the semiconductor fin, and a sidewall portion on a sidewall portion of the dielectric layer. The top portion of the gate electrode has a first work function, and the sidewall portion of the gate electrode has a second work function different from the first work function.

Abstract: An overlap mark set is provided to have at least a first and a second overlap marks both of which are located at the same pattern layer. The first overlap mark includes at least two sets of X-directional linear patterns, having a preset offset a1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset a1 therebetween. The second overlap mark includes at least two sets of X-directional linear patterns, having a preset offset b1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset b1 therebetween. The preset offsets a1 and b1 are not equal.

Abstract: A device includes a substrate, a semiconductor fin over the substrate, and a gate dielectric layer on a top surface and sidewalls of the semiconductor fin. A gate electrode is spaced apart from the semiconductor fin by the gate dielectric layer. The gate electrode includes a top portion over and aligned to the semiconductor fin, and a sidewall portion on a sidewall portion of the dielectric layer. The top portion of the gate electrode has a first work function, and the sidewall portion of the gate electrode has a second work function different from the first work function.

Abstract: An N work function metal for a gate stack of a field effect transistor (FinFET) and method of forming the same are provided. An embodiment FinFET includes a fin supported by a semiconductor substrate, the fin extending between a source and a drain and having a channel region, and a gate stack formed over the channel region of the fin, the gate stack including an N work function metal layer comprising an oxidation layer on opposing sides of a tantalum aluminide carbide (TaAlC) layer.

Abstract: An N work function metal for a gate stack of a field effect transistor (FinFET) and method of forming the same are provided. An embodiment FinFET includes a fin supported by a semiconductor substrate, the fin extending between a source and a drain and having a channel region, and a gate stack formed over the channel region of the fin, the gate stack including an N work function metal layer comprising an oxidation layer on opposing sides of a tantalum aluminide carbide (TaAlC) layer.

Abstract: A GRINSCH laser having an asymmetric configuration wherein the optical confinement is weighted more to the n-doped multilayer section than to the p-doped multilayer section. The GRINSCH laser can emit laser light at a wavelength ?=976 nm over a broad area with a beam power of 11.4 W at a 12 A bias current at a temperature of 20° C. Fabry-Perot and distributed Bragg reflector GRINSCH laser configurations are disclosed.

Abstract: An assembled wearable electronic device includes a first body, a second body and an engaging assembly. The first body has a primary system for providing the independent operation of the first body and producing a related first data. The second body has a secondary system and a fixing assembly. The secondary system is for providing the independent operation of the second body and producing a related second data. The engaging assembly is disposed at one of the first and second bodies. When the engaging assembly is located at a first position, the first and second bodies contact each other to be combined through the engaging assembly. When the engaging assembly moves to a second position, the first and second bodies are configured to be separated from each other. When the first and second bodies are connected to each other, the second data is read by the primary system.

Abstract: A device includes a substrate, a semiconductor fin over the substrate, and a gate dielectric layer on a top surface and sidewalls of the semiconductor fin. A gate electrode is spaced apart from the semiconductor fin by the gate dielectric layer. The gate electrode includes a top portion over and aligned to the semiconductor fin, and a sidewall portion on a sidewall portion of the dielectric layer. The top portion of the gate electrode has a first work function, and the sidewall portion of the gate electrode has a second work function different from the first work function.

Abstract: A device includes a substrate, a semiconductor fin over the substrate, and a gate dielectric layer on a top surface and sidewalls of the semiconductor fin. A gate electrode is spaced apart from the semiconductor fin by the gate dielectric layer. The gate electrode includes a top portion over and aligned to the semiconductor fin, and a sidewall portion on a sidewall portion of the dielectric layer. The top portion of the gate electrode has a first work function, and the sidewall portion of the gate electrode has a second work function different from the first work function.