Patents by Inventor Chin Lee
Chin Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240147311Abstract: Apparatus, methods, and computer-readable media for facilitating network slice based reselection using machine learning are disclosed herein. An example method for wireless communication at a UE includes predicting a next active PDU session of two or more PDU sessions based on next connection setup times for each PDU session. The next connection setup times may be estimated based on connection setup events occurring over a period. The example method also includes selecting a frequency channel to camp on based on the next active PDU session.Type: ApplicationFiled: November 2, 2022Publication date: May 2, 2024Inventors: Kuo-Chun LEE, Vishal DALMIYA, Arvind Vardarajan SANTHANAM, Shanshan WANG, Leena ZACHARIAS, Vaishakh RAO, Tom CHIN
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Publication number: 20240145450Abstract: The present disclosure generally relates to an electronic assembly. The electronic assembly may include a semiconductor package including a first surface, an opposing second surface, and a side wall. The electronic assembly may also include a printed circuit board coupled to the second surface of the semiconductor package. The electronic assembly may further include at least one passive component array including one or more passive components at least partially embedded in a mold layer, each passive component further including a first terminal and a second terminal, wherein the first terminal of the passive component may be coupled to the printed circuit board and the passive component array may be attached to the side wall of the semiconductor package.Type: ApplicationFiled: October 28, 2022Publication date: May 2, 2024Inventors: Chin Lee KUAN, Bok Eng CHEAH, Jackson Chung Peng KONG, Amit JAIN, Sameer SHEKHAR
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Patent number: 11974411Abstract: The present invention is related to a thin heat dissipation device and a method for manufacturing the same. The device of the present invention mainly comprises a hollow body having an enclosed chamber and a working fluid with which the enclosed chamber is filled. The enclosed chamber comprises a first fluid channel and a second fluid channel. The first and second fluid channels extend in the longitudinal direction of the hollow body, are juxtaposed in the width direction of the hollow body and communicated with each other, and an interface between the first fluid channel and the second fluid channel has a height of about 0.1 mm or less. As such, a novel capillary structure which is capable of greatly reducing the entire thickness, enhancing heat transfer efficiency and reducing cost and which is reliable and durable is provided.Type: GrantFiled: January 17, 2020Date of Patent: April 30, 2024Inventor: Ke Chin Lee
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Patent number: 11973261Abstract: An antenna structure with wide radiation bandwidth in a reduced physical space includes a metallic housing, a first feed portion, and a second feed portion. The metallic housing includes a metallic side frame and a metallic back board. The metallic side frame defines a slot, and first and second gaps. The metallic side frame between the first gap and one end of the slot forms a first radiation portion. The second gap divides the first radiation portion into first and second radiation sections. The first feed portion feeds current and signal to the first radiation section, and the first radiation section works in a GPS mode and a WIFI 2.4 GHz mode. The second feed portion feeds current and signal to the second radiation section, and the second radiation section works in a WIFI 5 GHz mode.Type: GrantFiled: January 15, 2021Date of Patent: April 30, 2024Assignee: Chiun Mai Communication Systems, Inc.Inventors: Kun-Lin Sung, Yung-Chin Chen, Yi-Chieh Lee
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Publication number: 20240136221Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip may comprise a first metal line disposed over a substrate. A via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. A first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. A first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Inventors: Shao-Kuan Lee, Hai-Ching Chen, Hsin-Yen Huang, Shau-Lin Shue, Cheng-Chin Lee
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Patent number: 11967446Abstract: An inductor is disclosed, the inductor comprising: a T-shaped magnetic core, being made of a material comprising an annealed soft magnetic metal material and having a base and a pillar integrally formed with the base, wherein ?CĂ—Hsat?1800, where ?C is a permeability of the T-shaped magnetic core, and Hsat (Oe) is a strength of the magnetic field at 80% of ?C0, where ?C0 is the permeability of the T-shaped magnetic core when the strength of the magnetic field is 0.Type: GrantFiled: January 4, 2021Date of Patent: April 23, 2024Assignee: CYNTEC CO., LTD.Inventors: Chun-Tiao Liu, Lan-Chin Hsieh, Tsung-Chan Wu, Chi-Hsun Lee, Chih-Siang Chuang
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Publication number: 20240128853Abstract: A power converter that properly copes with the wiring defects on a feedback path is shown. According to a control signal, a power driver couples an input voltage to an energy storage element to provide an output voltage that is down-converted from the input voltage. The output voltage is further converted into a feedback voltage by a feedback circuit, and is entered to an error amplifier with a reference voltage for generation of an amplified error. A control signal generator generates the control signal of the power driver according to the amplified error. The power converter specifically has a comparator, which is enabled in a soft-start stage till the output voltage reaches a stable status. The comparator compares the amplified error with a critical value. When the amplified error exceeds the critical value, the input voltage is disconnected from the energy storage element.Type: ApplicationFiled: December 22, 2022Publication date: April 18, 2024Inventors: Jung-Sheng CHEN, Chih-Chun CHUANG, Yong-Chin LEE
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Patent number: 11958750Abstract: Provided are a negative electrode active material which includes negative electrode active material particles which includes a silicon oxide (SiOx, 0<x?2); and at least one lithium silicate selected from Li2SiO3, Li2Si2O5, and Li4SiO4 in at least a part of the silicon oxide. The negative electrode active material particles have a maximum peak position by a Raman spectrum of more than 460 cm?1 and less than 500 cm?1. Also provided are a method of preparing the same, and a negative electrode and a lithium secondary battery including the negative electrode active material.Type: GrantFiled: May 20, 2021Date of Patent: April 16, 2024Assignee: SK On Co., Ltd.Inventors: Eunjun Park, Joon-Sup Kim, Gwi Ok Park, Jeongbae Yoon, Suk Chin Lee, Hansu Kim, Donghan Youn, Dong Jae Chung
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Patent number: 11963053Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may determine, via a first subscription of the UE, a trigger event for a conditional handover of the UE from a source network entity to a target network entity. The UE may determine, based at least in part on the trigger event, that a target band associated with the target network entity is not compatible with a serving band associated with a second subscription of the UE. The UE may store the trigger event for the conditional handover in a buffer of the UE. The UE may perform an action related to the conditional handover based at least in part on a condition being satisfied. Numerous other aspects are described.Type: GrantFiled: February 18, 2022Date of Patent: April 16, 2024Assignee: QUALCOMM IncorporatedInventors: Kuo-Chun Lee, Qingxin Chen, Arvind Vardarajan Santhanam, Reza Shahidi, Mouaffac Ambriss, Liangchi Hsu, Tom Chin
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Publication number: 20240115770Abstract: The present disclosure provides a tunable porous fibrous scaffold composition, comprising one or more modified glycosaminoglycans; and (ii) one or more extracellular matrix (ECM) proteins. The present disclosure also provides methods for preparing the tunable porous fibrous scaffold composition described herein.Type: ApplicationFiled: October 6, 2023Publication date: April 11, 2024Inventors: Su Chin Heo, Zizhao Li, Se-Hwan Lee
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Patent number: 11948883Abstract: A semiconductor device including a transistor on a substrate; an interlayer insulating layer on the transistor; a first metal-containing layer on the interlayer insulating layer; and a second metal-containing layer on the first metal-containing layer, wherein the second metal-containing layer includes a resistor, the resistor includes a first insulating layer on the first metal-containing layer; a resistor metal layer on the first insulating layer; and a second insulating layer on the resistor metal layer, and the resistor metal layer includes a recessed side surface.Type: GrantFiled: April 2, 2021Date of Patent: April 2, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Seonghun Lim, Wookyung You, Kyoungwoo Lee, Juyoung Jung, Il Sup Kim, Chin Kim, Kyoungpil Park, Jinhyung Park
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Publication number: 20240094059Abstract: A curved prism array applied to an infrared sensor wherein: the infrared sensor comprises at least an infrared sensing element which is used in detecting infrared signals within a solid-angled FOV and installed inside the curved prism array; the curved prism array has an incident focal plane and a plurality of emergent focal planes, both of which are not parallel with each other, such that infrared signals beyond the solid-angled FOV are received by the incident focal plane, refracted through one of the emergent focal planes and guided toward the infrared sensing element for expansion of the solid-angled FOV of the infrared sensing element.Type: ApplicationFiled: September 15, 2022Publication date: March 21, 2024Inventors: Wen-Chin CHEN, Ai-Huan LEE
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Patent number: 11935957Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.Type: GrantFiled: August 9, 2021Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
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Patent number: 11932714Abstract: A copolymer, a film composition and a composite material employing the same are provided. The copolymer is a copolymerization product of a composition, wherein the composition includes a monomer (a), a monomer (b) and a monomer (c). The monomer (a) is a compound having a structure represented by Formula (I), the monomer (b) is a compound having a structure represented by Formula (II), and the monomer (c) is a compound having a structure represented by Formula (III) wherein R1, R2, R3, R4, R5 and R6 are as defined in specification.Type: GrantFiled: July 22, 2022Date of Patent: March 19, 2024Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yen-Yi Chu, Yun-Ching Lee, Li-Chun Liang, Wei-Ta Yang, Hsiang-Chin Juan
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Patent number: 11934376Abstract: A database management engine provides a user interface that allows users to access and modify employee information in a database. The database includes entries for employees, and each database entry includes identifying information about the associated employee. A user can request to modify data within database entries, for instance in order to update information associated with an employee. Responsive to the request, the database management engine identifies liabilities associated with the database modification stemming from associated tax laws. Based on the identified tax liabilities, the engine computes the aggregate tax liability owed by the employer and/or employee. Before modifying a database entry, the engine modifies the user interface to include interface elements detailing the computed aggregate tax liability. The user explicitly can be required to confirm the database modification in view of the aggregate tax liability.Type: GrantFiled: March 29, 2023Date of Patent: March 19, 2024Assignee: ZENPAYROLL, INC.Inventors: Michael Kelly Sutton, Stephen Walter Hopkins, Matthew Charles Wilde, Alexander Scott Gerstein, Julia Hara Chin Lee, Michael Ryan Nierstedt, Nicholas Giancarlo Gervasi, Matan Zruya, Robert Douglas Gill, Jr., Bria Nicole Fincher, Ningjing Su, Ryan Kwong, Sheng Xiang Lei, Ketki Warudkar Duvvuru
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Patent number: 11935783Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.Type: GrantFiled: May 16, 2022Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Yen Huang, Shao-Kuan Lee, Cheng-Chin Lee, Hai-Ching Chen, Shau-Lin Shue
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Publication number: 20240087207Abstract: Disclosed herein are system, method, and computer program product embodiments for reducing GPU load by programmatically controlling shading rates in computer graphics. GPU load may be reduced by applying different shading rates to different screen regions. By reading the depth buffer of previous frames and performing image processing, thresholds may be calculated that control the shading rates. The approach may be run on any platform that supports VRS hardware and primitive- or image-based VRS. The approach may be applied on a graphics driver installed on a client device, in a firmware layer between hardware and a driver, in a software layer between a driver and an application, or in hardware on the client device. The approach is flexible and adaptable and calculates and sets the variable rate shading based on the graphics generated by an application without requiring the application developer to manually set variable rate shading.Type: ApplicationFiled: September 14, 2022Publication date: March 14, 2024Applicant: MediaTek Inc.Inventors: Po-Yu HUANG, Shih-Chin LIN, Jen-Jung CHENG, Tu-Hsiu LEE
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Publication number: 20240088023Abstract: An interconnect structure includes a dielectric layer, a first conductive feature, a hard mask layer, a conductive layer, and a capping layer. The first conductive feature is disposed in the dielectric layer. The hard mask layer is disposed on the first conductive feature. The conductive layer includes a first portion and a second portion, the first portion of the conductive layer is disposed over at least a first portion of the hard mask layer, and the second portion of the conductive layer is disposed over the dielectric layer. The hard mask layer and the conductive layer are formed by different materials. The capping layer is disposed on the dielectric layer and the conductive layer.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Inventors: Shao-Kuan LEE, Kuang-Wei YANG, Cherng-Shiaw TSAI, Cheng-Chin LEE, Ting-Ya LO, Chi-Lin TENG, Hsin-Yen HUANG, Hsiao-Kang CHANG, Shau-Lin SHUE
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Publication number: 20240087980Abstract: A semiconductor device includes a substrate, a dielectric layer disposed over the substrate, and an interconnect structure extending through the dielectric layer. The dielectric layer includes a low-k dielectric material which includes silicon carbonitride having a carbon content ranging from about 30 atomic % to about 45 atomic %. The semiconductor device further includes a thermal dissipation feature extending through the dielectric layer and disposed to be spaced apart from the interconnect structure.Type: ApplicationFiled: February 17, 2023Publication date: March 14, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kai-Fang CHENG, Cherng-Shiaw TSAI, Cheng-Chin LEE, Yen-Ju WU, Yen-Pin HSU, Li-Ling SU, Ming-Hsien LIN, Hsiao-Kang CHANG
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Patent number: 11923243Abstract: A method for manufacturing a semiconductor structure includes preparing a dielectric structure formed with trenches respectively defined by lateral surfaces of the dielectric structure, forming spacer layers on the lateral surfaces, filling an electrically conductive material into the trenches to form electrically conductive features, selectively depositing a blocking layer on the dielectric structure, selectively depositing a dielectric material on the electrically conductive features to form a capping layer, removing the blocking layer and the dielectric structure to form recesses, forming sacrificial features in the recesses, forming a sustaining layer to cover the sacrificial features; and removing the sacrificial features to obtain the semiconductor structure formed with air gaps confined by the sustaining layer and the spacer layers.Type: GrantFiled: August 30, 2021Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Yen Huang, Ting-Ya Lo, Shao-Kuan Lee, Chi-Lin Teng, Cheng-Chin Lee, Shau-Lin Shue, Hsiao-Kang Chang