Abstract: A method is provided for light shielding a charge storage device of an image sensor pixel that includes a photosensitive device and the charge storage device and a dielectric layer covering the photosensitive device and the charge storage device. The method includes performing etching of the dielectric layer to define an undercut volume beneath the dielectric layer and an access opening through the dielectric layer to the undercut volume, and performing physical vapor deposition (PVD) of a light blocking material to both: fill the undercut volume with the light blocking material to form a light blocking layer covering the charge storage device, and fill the access opening with the light blocking material to form a light blocking plug. An image sensor pixel formed by such a process, and an image sensor comprising an array of image sensor pixels, are also disclosed.

Abstract: A system and method for managing a respiratory condition of a user is disclosed. The system includes an oxygen concentrator having a compression system configured to generate oxygen enriched air for delivery to the user. A physiological sensor is configured to collect physiological data of the user. The physiological data is of one or more data types. An operational sensor is configured to collect operational data of the oxygen concentrator during operation of the oxygen concentrator. The operational data is of one or more data types. A processor is configured to receive the collected physiological data and the operational data and compute a summary parameter for values of each data type. The processor is also configured to compute a health score from the summary parameter values.

Abstract: A chip package and method for fabricating the same are provided that includes a power delivery network (PDN) with non-uniform electrical conductance. The electrical conductance through each current path of the PDN may be selected to balance the distribution of current flow across the current paths through the chip package, thus compensating for areas of high and low current draw found in conventional designs.

Abstract: The invention relates to a modular building structure (10) comprising: a framework (12) including a plurality of rods (14) and connectors (16) to interconnect the plurality of rods (14) together, the framework (12) comprising empty spaces bordered by corresponding rods (14) of said plurality of rods; a plurality of panels (20), wherein one panel (20) is mounted inside each empty space and connected to the framework (12) in order to create an interior (40), an air chamber layer (44) inside which air may circulate, said air chamber layer (44) forming at least a portion of an outer surface of said interior (40), at least one upper valve system (46a) mounted in the upper portion of the structure (10), and at least one lower valve system (46b) mounted in the lower portion of the structure (10).

Abstract: Technologies for low-leakage and low series resistance on-chip capacitors are disclosed. In the illustrative embodiment, each electrode of a capacitor is formed from two metal layers and vias between the metal layers. A high-k dielectric layer is between the metal layers. The electrodes are displaced relative to each other on the plane defined by the high-k dielectric layer. As a result, electric field lines of the capacitor are parallel to the high-k dielectric layer. The electrodes can be displaced from each other by more than the thickness of the high-k dielectric layer, reducing the leakage current through the high-k dielectric layer as compared to a capacitor with field lines perpendicular to the high-k dielectric layer. Such a capacitor may be used to provide power to circuits in a low-power state with little leakage current and/or may be used to absorb radiofrequency (RF) interference.

Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate and a device region formed over the substrate. The semiconductor structure further includes an interconnect structure formed over the device region and a first passivation layer formed over the interconnect structure. The semiconductor structure also includes a metal pad formed over and extending into the first passivation layer and a second passivation layer formed over the first passivation layer. The second passivation layer includes a thermal conductive material, and the thermal conductivity of the thermal conductive material is higher than 4 W/mK.

Abstract: In one embodiment, a self-aligned via is presented. In one embodiment, an inhibitor layer is selectively deposited on the lower conductive region. In one embodiment, a dielectric is selectively deposited on the lower conductive region. In one embodiment, the deposited dielectric may be selectively etched. In one embodiment, an inhibitor is selectively deposited on the lower dielectric region. In one embodiment, a dielectric is selectively deposited on the lower dielectric region. In one embodiment, the deposited dielectric over the lower conductive region has a different etch rate than the deposited dielectric over the lower dielectric region which may lead to a via structure that is aligned with the lower conductive region.

Abstract: A method of manufacturing a semiconductor device includes forming a gate trench over a semiconductor substrate, depositing a gate dielectric layer and a work function layer in the gate trench, depositing a capping layer over the work function layer, passivating a surface portion of the capping layer to form a passivation layer, removing the passivation layer, depositing a fill layer in the gate trench, recessing the fill layer and the capping layer, and forming a contact metal layer above the capping layer in the gate trench.

Abstract: An apparatus, system, and method for improved thermal design power (TDP) range are provided. A device includes a first voltage regulator configured to provide first voltage of a first voltage value, a second voltage regulator configured to provide a second voltage of a second, different voltage value, a first capacitor electrically coupled between a first output of the first voltage regulator and a ground, a second capacitor electrically coupled between a second output of the second voltage regulator and the ground, a first switch electrically coupled between the first output and the second output, a second switch situated in parallel with the first switch, the second switch electrically coupled between the first output and the second output, and a controller configured to provide control signals that control the first voltage regulator, the second voltage regulator, the first switch, and the second switch.

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.

Abstract: A method and system of responding to adverse environmental conditions local to a user of an oxygen concentrator is disclosed. Physiological data of the user is collected. Operational data of the oxygen concentrator is collected during operation of the oxygen concentrator. Environment data local to the oxygen concentrator is collected. Based on the collected environmental data, it is determined whether adverse environmental conditions exist local to the oxygen concentrator. The collected physiological, operational, and environmental data are analyzed to determine a responsive action to the determined adverse environmental conditions. The responsive action is communicated to the user.

Abstract: A method for manufacturing a semiconductor device includes: forming a first feature and a second feature extending in a normal direction transverse to a substrate; directionally depositing a dielectric material upon the features at an inclined angle relative to the normal direction so as to form a cap layer including a top portion disposed on a top surface of each of the features, and two opposite wall portions extending downwardly from two opposite ends of the top portion to partially cover two opposite lateral surfaces of each of the features, respectively, the cap layer on the first feature being spaced apart from the cap layer on the second feature; forming a sacrificial feature in a recess between the features; forming a sustaining layer to cover the sacrificial feature; and removing the sacrificial feature to form an air gap.

Abstract: A method is provided for light shielding a charge storage device of an image sensor pixel that includes a photosensitive device and the charge storage device and a dielectric layer covering the photosensitive device and the charge storage device. The method includes performing etching of the dielectric layer to define an undercut volume beneath the dielectric layer and an access opening through the dielectric layer to the undercut volume, and performing physical vapor deposition (PVD) of a light blocking material to both: fill the undercut volume with the light blocking material to form a light blocking layer covering the charge storage device, and fill the access opening with the light blocking material to form a light blocking plug. An image sensor pixel formed by such a process, and an image sensor comprising an array of image sensor pixels, are also disclosed.

Abstract: An efficient fabrication technique, including an optional design step, is used to create highly customizable wearable electronics. The method of fabrication utilizes rapid laser machining and adhesion-controlled soft materials. The method produces well-aligned, multi-layered materials created from 2D and 3D elements that stretch and bend while seamlessly integrating with rigid components such as microchip integrated circuits (IC), discrete electrical components, and interconnects. The design step can be used to create a 3D device that conforms to different-shaped body parts. These techniques are applied using commercially available materials. These methods enable custom wearable electronics while offering versatility in design and functionality for a variety of bio-monitoring applications.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.

Abstract: Disclosed herein are methods for the detection of the presence of sperm DNA fragmentation in a semen sample. The methods include embedding of sperm cells of the semen sample in a gel, denaturing DNA of the sperm cells, and lysing the nuclear proteins of the sperm cells. The present method includes an ionic surfactant sodium dodycyl sulfate (SDS) and a chaotropic agent urea in the lysis solution for releasing DNA from protamine of chromosome, which significantly reduces the time required for lysis. A kit for detecting sperm DNA fragmentation in a semen sample is also disclosed.

Abstract: An overvoltage protection circuit which can be applied to a motor controller is provided. The overvoltage protection circuit is coupled to an input terminal for receiving an input voltage. The overvoltage protection circuit comprises a switch circuit, a controller, and a comparing unit. When the input voltage is greater than a first voltage, a discharging mechanism is forced to start so as to suppress a voltage spike. When the input voltage is less than a second voltage, the discharging mechanism is closed so as to operate normally.

Abstract: A database management engine provides a user interface that allows users to access and modify employee information in a database. The database includes entries for employees, and each database entry includes identifying information about the associated employee. A user can request to modify data within database entries, for instance in order to update information associated with an employee. Responsive to the request, the database management engine identifies liabilities associated with the database modification stemming from associated tax laws. Based on the identified tax liabilities, the engine computes the aggregate tax liability owed by the employer and/or employee. Before modifying a database entry, the engine modifies the user interface to include interface elements detailing the computed aggregate tax liability. The user explicitly can be required to confirm the database modification in view of the aggregate tax liability.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.