Patents by Inventor Chin-Long Chen

Chin-Long Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200242273
    Abstract: A memory chip comprises a first memory controller, a first data storage zone, a security unit and an address configuration unit. The first data storage zone is coupled to the first memory controller, and represented by a first physical address range. The security unit is coupled to the first memory controller. The address configuration unit is coupled to the first memory controller. The memory chip is configured to be coupled between a host controller and another memory chip. The another memory chip comprises a second data storage zone represented by a second physical address range. The address configuration unit records one or more relationships of a logical address range corresponding to the first physical address range and the second physical address range. The security unit is configured to encrypt and decrypt data in the first data storage zone and the second data storage zone.
    Type: Application
    Filed: December 24, 2019
    Publication date: July 30, 2020
    Inventors: Kuen-Long CHANG, Chia-Jung CHEN, Chin-Hung CHANG, Ken-Hui CHEN
  • Publication number: 20200241768
    Abstract: A memory device comprises a memory array with I/O path and security circuitry coupled to the I/O path of the memory array. The memory device comprises control circuitry, responsive to configuration data, to invoke the security circuitry. The memory device comprises a configuration store, storing the configuration data accessible by the control circuitry to specify location and size of a security memory region in the memory array. Responsive to an external command and the configuration data, the control circuitry can be configured to invoke the security circuitry on an operation specified in the external command in response to accesses into the security memory region, or to not invoke the security circuitry in response to accesses to outside the security memory region.
    Type: Application
    Filed: January 28, 2019
    Publication date: July 30, 2020
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ken-Hui CHEN, Kuen-Long CHANG, Chin-Hung CHANG, Yu-Chen WANG
  • Patent number: 10700176
    Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Chin-Chi Wang, Chi-Wen Liu, Wai-Yi Lien, Chih-Hao Wang
  • Publication number: 20200186339
    Abstract: A system and method use a physical unclonable function in a PUF circuit on an integrated circuit to generate a security key, and stabilize the security key by storage in a set of nonvolatile memory cells. The stabilized security key is moved from the set of nonvolatile memory cells to a cache memory, and utilized as stored in the cache memory in a security protocol. Also, data transfer from the PUF circuit to the set of nonvolatile memory cells can be disabled after using the PUF circuit to produce the security key, at a safe time, such as after the security key has been moved from the set of nonvolatile memory cells to the cache memory.
    Type: Application
    Filed: February 18, 2020
    Publication date: June 11, 2020
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung HUNG, Kuen-Long CHANG, Ken-Hui CHEN, Shih-Chang HUANG, Chin-Hung CHANG, Chen-Chia FAN
  • Patent number: 10680809
    Abstract: A system including a host and a guest device, where the guest device can be implemented on a single packaged integrated circuit or a multichip circuit and have logic to use a physical unclonable function to produce a security key. The device can include logic on the guest to provide the PUF key to the host in a secure manner. The physical unclonable function can use entropy derived from non-volatile memory cells to produce the initial key. Logic is described to disable changes to PUF data, and thereby freeze the key after it is stored in the set.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: June 9, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuen-Long Chang, Ken-Hui Chen, Chin-Hung Chang
  • Publication number: 20200075742
    Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.
    Type: Application
    Filed: October 24, 2019
    Publication date: March 5, 2020
    Inventors: Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Chin-Chi Wang, Chi-Wen Liu, Wai-Yi Lien, Chih-Hao Wang
  • Patent number: 10483367
    Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Chin-Chi Wang, Chi-Wen Liu, Wai-Yi Lien, Chih-Hao Wang
  • Patent number: 10291258
    Abstract: Systems, apparatuses, and methods for generating error correction codes (ECCs) with two check symbols are disclosed. In one embodiment, a system receives a data word of length N?2 symbols, wherein N is a positive integer greater than 2, wherein each symbol has m bits, and wherein m is positive integer. The system generates a code word of length N symbols from the data word in accordance with a linear code defined by a parity check matrix. The parity check matrix is generated based on powers of ?, wherein ? is equal to ? raised to the (2m/4?1) power, ? is equal to a raised to the (2m/2+1) power, and ? is a primitive element of GF(2m). In another embodiment, the system receives a (N, N?2) code word and decodes the code word by generating a syndrome S from the code word using the parity check matrix.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: May 14, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Chin-Long Chen
  • Publication number: 20180343018
    Abstract: Systems, apparatuses, and methods for generating error correction codes (ECCs) with two check symbols are disclosed. In one embodiment, a system receives a data word of length N?2 symbols, wherein N is a positive integer greater than 2, wherein each symbol has m bits, and wherein m is positive integer. The system generates a code word of length N symbols from the data word in accordance with a linear code defined by a parity check matrix. The parity check matrix is generated based on powers of ?, wherein ? is equal to ? raised to the (2m/4?1) power, ? is equal to a raised to the (2m/2+1) power, and ? is a primitive element of GF(2m). In another embodiment, the system receives a (N, N?2) code word and decodes the code word by generating a syndrome S from the code word using the parity check matrix.
    Type: Application
    Filed: May 25, 2017
    Publication date: November 29, 2018
    Inventor: Chin-Long Chen
  • Publication number: 20120257296
    Abstract: A color filter substrate includes a transparent plate, a black matrix, a plurality of filter layers, a plurality of first support pads, and a transparent conductive layer. The transparent plate has a plane. The black matrix is disposed on the plane and has a plurality of grid areas. The filter layers are disposed on the plane and located in the grid areas respectively. The first support pads partially cover the black matrix. Each of the first support pads is located among adjacent four filter layers. An area on the black matrix covered by each of the first support pads is in a shape of a cross. The first support pads are connected to the filter layers. Each first support pad includes a first pad layer, a second pad layer, and a third pad layer. The transparent conductive layer covers the filter layers, the first support pads, and the black matrix.
    Type: Application
    Filed: July 15, 2011
    Publication date: October 11, 2012
    Inventors: Der-Chun WU, Chih-Ho Lien, Chin-Long Chen, Shang-Chih Wu
  • Patent number: 8033964
    Abstract: A dumbbell assembly includes a tube, a rod rotatably received in the tube, and two rotary units respectively connected to two ends of the rod. Each rotary unit has a wing to which multiple weight members are connected. The rod is rotated relative to the tube and the wings together with the weight members are rotated to generate centrifugal forces which apply to the user's muscles.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: October 11, 2011
    Inventor: Chin-Long Chen
  • Patent number: 7904195
    Abstract: A method for prognostic maintenance in semiconductor manufacturing equipments is disclosed. The said method comprising: collecting a plurality of raw data from the default detection and classification system for equipments, preprocessing the raw data, using the neural network model (NN model) to find a plurality of health indices, generating health information by using the principal component analysis (PCA) to identify the health indices, and using the partial least square discriminated analysis (PLS-DA) to find a health report. The health report provides the engineers with current risk levels of equipments. By the health report, the engineers can initiate prognostic maintenance and repair the equipments early.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: March 8, 2011
    Assignee: Inotera Memories, Inc.
    Inventors: Chung-Pei Chao, Chin-Long Chen
  • Publication number: 20090306804
    Abstract: A method for prognostic maintenance in semiconductor manufacturing equipments is disclosed. The said method comprising: collecting a plurality of raw data from the default detection and classification system for equipments, preprocessing the raw data, using the neural network model (NN model) to find a plurality of health indices, generating health information by using the principal component analysis (PCA) to identify the health indices, and using the partial least square discriminated analysis (PLS-DA) to find a health report. The health report provides the engineers with current risk levels of equipments. By the health report, the engineers can initiate prognostic maintenance and repair the equipments early.
    Type: Application
    Filed: October 1, 2008
    Publication date: December 10, 2009
    Applicant: INOTERA MEMORIES, INC.
    Inventors: CHUNG-PEI CHAO, CHIN-LONG CHEN
  • Patent number: 7627114
    Abstract: Modular reduction and modular multiplication for large numbers are required operations in public key cryptography. Moreover, efficient execution of these two operations is important to achieve high performance levels in cryptographic engines and processes. The present invention uses multiplication and addition instead of using division and subtraction to perform modular arithmetic. The present invention also achieves some of its advantages through processing which begins with the high order bits coupled with judicious observations pertaining to circumstances under which carry output signals from addition operations are generated. These carry output signals are used to provide corrections which thus enable the use of the higher order bits and the efficiencies that such use engenders. Additionally, unlike other methods, the present invention avoids the baggage of preprocessing and post processing operations.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: December 1, 2009
    Assignee: International Business Machines Corporation
    Inventor: Chin-Long Chen
  • Patent number: 7487425
    Abstract: Byte or symbol organized linear block codes are optimized in terms of reducing the number of ones in their parity check matrices by means of symbol column transformations carried out by multiplication by non-singular matrices. Each optimized symbol column preferably, and probably necessarily, includes a submatrix which is the identity matrix which contributes to low weight check matrices and also to simplified decoding procedures and apparatus. Since circuit cost and layout area are proportional to the number of Exclusive-OR gates which is determined by the number of ones in the check matrix, it is seen that the reduction procedures carried out in accordance with the present invention solve significant problems that are particularly applicable in the utilization of byte organized semiconductor memory systems. Reduced weight coding systems are also generated in accordance with weight reducing procedures used in conjunction with modified Reed Solomon codes.
    Type: Grant
    Filed: May 17, 1993
    Date of Patent: February 3, 2009
    Assignee: International Business Machines Corporation
    Inventor: Chin-Long Chen
  • Patent number: 7243293
    Abstract: An (18, 9) error correction code that is simultaneously double error correcting and triple error detecting is disclosed. The code is defined by the following parity check matrix: ? 1 3 ? ? ? ? 1 6 ? ? ? 1 12 ? ? ? 1 7 ? ? ? ? 1 14 ? ? ? 1 11 ? ? ? 1 5 ? ? ? 1 1 ? ? ? 1 2 ? ? ? 1 4 ? ? ? 1 8 ? ? ? ? 1 16 ? ? ? 1 15 ? ? ? 1 13 ? ? ? 1 9 ? ? ? 0 ? 1 ? ? ? 1 10 ? ? 1 1 , where ? is a root of the polynomial x17?1 in the finite field of 256 elements. Logic circuitry for efficiently determining the locations of single and double errors as well as for detecting the presence of uncorrectable errors is also disclosed.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: July 10, 2007
    Assignee: International Business Machines Corporation
    Inventor: Chin-Long Chen
  • Patent number: 7171591
    Abstract: An error correction code for encoding the presence of a special uncorrectable error as well as its type. In the encoder, modification logic modifies the regular data symbols to indicate the type of special uncorrectable error. The encoder appends to the regular data symbols a special uncorrectable error symbol indicating the presence of a special uncorrectable error to form an extended data word, which is encoded to generate a code word. In the decoder, a syndrome generator generates a syndrome vector using an assumed value for the special uncorrectable error symbol indicating the absence of a special uncorrectable error, while a syndrome decoder determines the presence of the special uncorrectable error by determining the presence of an error in the assumed value of the special uncorrectable error symbol. By so using its error detection logic, the decoder makes it unnecessary to actually store or transmit the special uncorrectable error symbol.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: January 30, 2007
    Assignee: International Business Machines Corporation
    Inventor: Chin-Long Chen
  • Publication number: 20060286804
    Abstract: A method for forming a patterned material layer comprises the following steps. First, a material layer is formed on a substrate, and then a patterned positive photoresist layer is formed on the material layer. Next, the material layer is etched by using the patterned positive photoresist layer as a mask. Afterwards, a developing process is performed to remove the patterned positive photoresist layer. As mentioned above, the cost by using the method of the present invention can be reduced.
    Type: Application
    Filed: June 15, 2005
    Publication date: December 21, 2006
    Inventors: Chuan-Yi Wu, Chin-Long Chen, Yung-Chia Kuan
  • Patent number: 7093183
    Abstract: Error correction and detection codes are designed with several properties: the ability to perform error correction and detection operations via syndrome generation in multiple cycles of information delivery from a source such as a set of memory chips; a code structure which is cooperatively designed in terms of the bits-per-chip architecture of a set of memory chips so as to provide enhanced robustness in the face of bus line and chip failures; and a structured parity check matrix which provides circuits which are cheaper, take up less room, and are faster than standard designs.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: August 15, 2006
    Assignee: International Business Machines Corporation
    Inventor: Chin-Long Chen
  • Patent number: 7080110
    Abstract: The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: July 18, 2006
    Assignee: International Business Machines Corporation
    Inventors: Chin-Long Chen, Vincenzo Condorelli, Camil Fayad