Abstract: A method for flattening a three-dimensional shoe upper template is provided. The method includes providing a three-dimensional last model, obtaining a three-dimensional grid model, obtaining a three-dimensional thickened grid model, obtaining a two-dimensional initial-value grid model, and obtaining a two-dimensional grid model with the smallest energy value. A system and a non-transitory computer-readable medium for performing the method are also provided. The method makes it possible to precisely flatten a three-dimensional last model with a non-developable surface and thereby convert the three-dimensional last model into a two-dimensional grid model.

Abstract: Systems, apparatuses, and methods for generating error correction codes (ECCs) with two check symbols are disclosed. In one embodiment, a system receives a data word of length N?2 symbols, wherein N is a positive integer greater than 2, wherein each symbol has m bits, and wherein m is positive integer. The system generates a code word of length N symbols from the data word in accordance with a linear code defined by a parity check matrix. The parity check matrix is generated based on powers of ?, wherein ? is equal to ? raised to the (2m/4?1) power, ? is equal to a raised to the (2m/2+1) power, and ? is a primitive element of GF(2m). In another embodiment, the system receives a (N, N?2) code word and decodes the code word by generating a syndrome S from the code word using the parity check matrix.

Abstract: Systems, apparatuses, and methods for generating error correction codes (ECCs) with two check symbols are disclosed. In one embodiment, a system receives a data word of length N?2 symbols, wherein N is a positive integer greater than 2, wherein each symbol has m bits, and wherein m is positive integer. The system generates a code word of length N symbols from the data word in accordance with a linear code defined by a parity check matrix. The parity check matrix is generated based on powers of ?, wherein ? is equal to ? raised to the (2m/4?1) power, ? is equal to a raised to the (2m/2+1) power, and ? is a primitive element of GF(2m). In another embodiment, the system receives a (N, N?2) code word and decodes the code word by generating a syndrome S from the code word using the parity check matrix.

Abstract: A color filter substrate includes a transparent plate, a black matrix, a plurality of filter layers, a plurality of first support pads, and a transparent conductive layer. The transparent plate has a plane. The black matrix is disposed on the plane and has a plurality of grid areas. The filter layers are disposed on the plane and located in the grid areas respectively. The first support pads partially cover the black matrix. Each of the first support pads is located among adjacent four filter layers. An area on the black matrix covered by each of the first support pads is in a shape of a cross. The first support pads are connected to the filter layers. Each first support pad includes a first pad layer, a second pad layer, and a third pad layer. The transparent conductive layer covers the filter layers, the first support pads, and the black matrix.

Abstract: A dumbbell assembly includes a tube, a rod rotatably received in the tube, and two rotary units respectively connected to two ends of the rod. Each rotary unit has a wing to which multiple weight members are connected. The rod is rotated relative to the tube and the wings together with the weight members are rotated to generate centrifugal forces which apply to the user's muscles.

Abstract: A method for prognostic maintenance in semiconductor manufacturing equipments is disclosed. The said method comprising: collecting a plurality of raw data from the default detection and classification system for equipments, preprocessing the raw data, using the neural network model (NN model) to find a plurality of health indices, generating health information by using the principal component analysis (PCA) to identify the health indices, and using the partial least square discriminated analysis (PLS-DA) to find a health report. The health report provides the engineers with current risk levels of equipments. By the health report, the engineers can initiate prognostic maintenance and repair the equipments early.

Abstract: A method for prognostic maintenance in semiconductor manufacturing equipments is disclosed. The said method comprising: collecting a plurality of raw data from the default detection and classification system for equipments, preprocessing the raw data, using the neural network model (NN model) to find a plurality of health indices, generating health information by using the principal component analysis (PCA) to identify the health indices, and using the partial least square discriminated analysis (PLS-DA) to find a health report. The health report provides the engineers with current risk levels of equipments. By the health report, the engineers can initiate prognostic maintenance and repair the equipments early.

Abstract: Modular reduction and modular multiplication for large numbers are required operations in public key cryptography. Moreover, efficient execution of these two operations is important to achieve high performance levels in cryptographic engines and processes. The present invention uses multiplication and addition instead of using division and subtraction to perform modular arithmetic. The present invention also achieves some of its advantages through processing which begins with the high order bits coupled with judicious observations pertaining to circumstances under which carry output signals from addition operations are generated. These carry output signals are used to provide corrections which thus enable the use of the higher order bits and the efficiencies that such use engenders. Additionally, unlike other methods, the present invention avoids the baggage of preprocessing and post processing operations.

Abstract: Byte or symbol organized linear block codes are optimized in terms of reducing the number of ones in their parity check matrices by means of symbol column transformations carried out by multiplication by non-singular matrices. Each optimized symbol column preferably, and probably necessarily, includes a submatrix which is the identity matrix which contributes to low weight check matrices and also to simplified decoding procedures and apparatus. Since circuit cost and layout area are proportional to the number of Exclusive-OR gates which is determined by the number of ones in the check matrix, it is seen that the reduction procedures carried out in accordance with the present invention solve significant problems that are particularly applicable in the utilization of byte organized semiconductor memory systems. Reduced weight coding systems are also generated in accordance with weight reducing procedures used in conjunction with modified Reed Solomon codes.

Abstract: An (18, 9) error correction code that is simultaneously double error correcting and triple error detecting is disclosed. The code is defined by the following parity check matrix: ? 1 3 ? ? ? ? 1 6 ? ? ? 1 12 ? ? ? 1 7 ? ? ? ? 1 14 ? ? ? 1 11 ? ? ? 1 5 ? ? ? 1 1 ? ? ? 1 2 ? ? ? 1 4 ? ? ? 1 8 ? ? ? ? 1 16 ? ? ? 1 15 ? ? ? 1 13 ? ? ? 1 9 ? ? ? 0 ? 1 ? ? ? 1 10 ? ? 1 1 , where ? is a root of the polynomial x17?1 in the finite field of 256 elements. Logic circuitry for efficiently determining the locations of single and double errors as well as for detecting the presence of uncorrectable errors is also disclosed.

Abstract: An error correction code for encoding the presence of a special uncorrectable error as well as its type. In the encoder, modification logic modifies the regular data symbols to indicate the type of special uncorrectable error. The encoder appends to the regular data symbols a special uncorrectable error symbol indicating the presence of a special uncorrectable error to form an extended data word, which is encoded to generate a code word. In the decoder, a syndrome generator generates a syndrome vector using an assumed value for the special uncorrectable error symbol indicating the absence of a special uncorrectable error, while a syndrome decoder determines the presence of the special uncorrectable error by determining the presence of an error in the assumed value of the special uncorrectable error symbol. By so using its error detection logic, the decoder makes it unnecessary to actually store or transmit the special uncorrectable error symbol.

Abstract: A method for forming a patterned material layer comprises the following steps. First, a material layer is formed on a substrate, and then a patterned positive photoresist layer is formed on the material layer. Next, the material layer is etched by using the patterned positive photoresist layer as a mask. Afterwards, a developing process is performed to remove the patterned positive photoresist layer. As mentioned above, the cost by using the method of the present invention can be reduced.

Abstract: Error correction and detection codes are designed with several properties: the ability to perform error correction and detection operations via syndrome generation in multiple cycles of information delivery from a source such as a set of memory chips; a code structure which is cooperatively designed in terms of the bits-per-chip architecture of a set of memory chips so as to provide enhanced robustness in the face of bus line and chip failures; and a structured parity check matrix which provides circuits which are cheaper, take up less room, and are faster than standard designs.

Abstract: The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations.

Abstract: Disclosed is preservation structure and preservation repository using the same. The preservation structure is constituted by a porous two-dimensional or three-dimensional solid structure with a slackness nature and a variety of nano-materials being uniformly distributed over the surface of the porous two-dimensional or three-dimensional solid structure, and is used to preserve an article therein over a long period of time. The freshness of the article is retained by making a direct contact between the nano-materials and the article. The usage of term or the period of preservation for the article is prolonged by placing the article needing to be preserved in the preservation repository.

Abstract: Symbol level multi-cycle error correction and detection coding systems are developed and deployed in computer memory architectures resulting in an increase in robustness in terms of single bus line failures having no effect on the robustness of the coding technique and capabilities. The multi-cycle symbol level error correction techniques of the present invention also provide a mechanism for reducing the pin-out requirements for memory chips and dual in-line memory modules. The resulting ECC circuitry is thus simpler and consumes less real estate.

Abstract: The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design which includes a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations.

Abstract: The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations.

Abstract: The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations.

Abstract: Finite field elements from the Galois field GF(2k) are represented as polynomials with binary valued coefficients. As such, multiplication in the field is defined modulo an irreducible polynomial of degree k?1. One of the multiplicands is treated in blocks of polynomials of degree n?1 so that the multiplier operates over T cycles where k=nT. If k is not a composite number to start with, higher order terms are added, so that multipliers are now constructable even when k is prime. Since n<k, the construction of the needed multiplier circuits are much simpler. Designers are now provided with an opportunity of easily trading off circuit speed for circuit complexity in an orderly and structured fashion.