Patents by Inventor Chin-Long Chen
Chin-Long Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050188209Abstract: The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations.Type: ApplicationFiled: December 19, 2000Publication date: August 25, 2005Applicant: International Business Machines CorporationInventors: Chin-Long Chen, Edward Chencinski, Vincenzo Condorelli, Leonard Fogell, Samir Patel
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Publication number: 20050185791Abstract: The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations.Type: ApplicationFiled: December 19, 2000Publication date: August 25, 2005Applicant: International Business Machines CorporationInventors: Chin-Long Chen, Vincenzo Condorelli, Camil Fayad
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Publication number: 20050188292Abstract: An error correction code for encoding the presence of a special uncorrectable error as well as its type. In the encoder, modification logic modifies the regular data symbols to indicate the type of special uncorrectable error. The encoder appends to the regular data symbols a special uncorrectable error symbol indicating the presence of a special uncorrectable error to form an extended data word, which is encoded to generate a code word. In the decoder, a syndrome generator generates a syndrome vector using an assumed value for the special uncorrectable error symbol indicating the absence of a special uncorrectable error, while a syndrome decoder determines the presence of the special uncorrectable error by determining the presence of an error in the assumed value of the special uncorrectable error symbol. By so using its error detection logic, the decoder makes it unnecessary to actually store or transmit the special uncorrectable error symbol.Type: ApplicationFiled: December 23, 2003Publication date: August 25, 2005Applicant: International Business Machines CorporationInventor: Chin-Long Chen
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Patent number: 6929995Abstract: A polysilicon layer and a first patterned photoresist layer are formed on a substrate. An ultraviolet curing process is performed to cure the first patterned photoresist layer. Then, a gate structure is formed by using the first patterned photoresist layer as a hard mask. A second patterned photoresist layer is formed on the substrate. The second patterned photoresist layer, the cured remaining first patterned photoresist layer and the gate form two openings alongside the gate structure. Finally, via the openings, two consecutive ion implantation processes are performed to form a double diffuse drain (DDD) structure.Type: GrantFiled: November 27, 2003Date of Patent: August 16, 2005Assignee: United Microelectronics Corp.Inventor: Chin-Long Chen
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Publication number: 20050149834Abstract: An (18, 9) error correction code that is simultaneously double error correcting and triple error detecting is disclosed. The code is defined by the following parity check matrix: B 3 B 6 B 12 ? 7 ? 14 ? 11 ? 5 ? 1 B 2 1 1 1 1 1 1 1 1 1 ? 4 B 8 B 16 ? 15 ? 13 ? 9 0 ? 10 1 1 1 1 1 1 1 1 1 1 , where ? is a root of the polynomial x17?1 in the finite field of 256 elements. Logic circuitry for efficiently determining the locations of single and double errors as well as for detecting the presence of uncorrectable errors is also disclosed.Type: ApplicationFiled: December 23, 2003Publication date: July 7, 2005Applicant: International Business Machines CorporationInventor: Chin-Long Chen
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Patent number: 6914983Abstract: The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations.Type: GrantFiled: December 19, 2000Date of Patent: July 5, 2005Assignee: International Business Machines CorporationInventors: Chin-Long Chen, Vincenzo Condorelli, Camil Fayad
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Publication number: 20050118768Abstract: A polysilicon layer and a first patterned photoresist layer are formed on a substrate. An ultraviolet curing process is performed to cure the first patterned photoresist layer. Then, a gate structure is formed by using the first patterned photoresist layer as a hard mask. A second patterned photoresist layer is formed on the substrate. The second patterned photoresist layer, the cured remaining first patterned photoresist layer and the gate form two openings alongside the gate structure. Finally, via the openings, two consecutive ion implantation processes are performed to form a double diffuse drain (DDD) structure.Type: ApplicationFiled: November 27, 2003Publication date: June 2, 2005Inventor: Chin-Long Chen
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Publication number: 20040210614Abstract: The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations.Type: ApplicationFiled: May 7, 2004Publication date: October 21, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chin-Long Chen, Vincenzo Condorelli, Camil Fayad
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Patent number: 6804696Abstract: The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design which includes a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations.Type: GrantFiled: December 19, 2000Date of Patent: October 12, 2004Assignee: International Business Machines CorporationInventors: Chin-Long Chen, Vincenzo Condorelli, Camil Fayad
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Patent number: 6763365Abstract: The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations.Type: GrantFiled: December 19, 2000Date of Patent: July 13, 2004Assignee: International Business Machines CorporationInventors: Chin-Long Chen, Vincenzo Condorelli, Camil Fayad
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Publication number: 20040120516Abstract: Modular reduction and modular multiplication for large numbers are required operations in public key cryptography. Moreover, efficient execution of these two operations is important to achieve high performance levels in cryptographic engines and processes. The present invention uses multiplication and addition instead of using division and subtraction to perform modular arithmetic. The present invention also achieves some of its advantages through processing which begins with the high order bits coupled with judicious observations pertaining to circumstances under which carry output signals from addition operations are generated. These carry output signals are used to provide corrections which thus enable the use of the higher order bits and the efficiencies that such use engenders. Additionally, the method of the present invention recognizes special circumstances that are employed to speed up processing.Type: ApplicationFiled: December 23, 2002Publication date: June 24, 2004Applicant: International Business Machines CorporationInventors: Chin-Long Chen, Tamas L. Visegrady
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Patent number: 6751769Abstract: A method of detecting double-symbol errors and correcting single-symbol errors in a data stream being transmitted in a computer system, e.g., from a memory array to a memory controller. The method includes decoding the data stream which was encoded using a logic circuit which had, as inputs, the data being sent and two address parity bits derived from the system address of the data. Data retrieved from the wrong address can be detected by this code. The logic circuit is described by a parity-check matrix for this (146,130) code comprising 128 data bits, 16 check bits, and 2 address parity bits. Although the symbol width of the code is four bits, the code can also be used effectively in memory systems where the memory chip width is eight bits.Type: GrantFiled: January 23, 2003Date of Patent: June 15, 2004Assignee: International Business Machines CorporationInventors: Chin-Long Chen, R. Brett Tremaine, Michael E. Wazlowski
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Publication number: 20040066934Abstract: Modular reduction and modular multiplication for large numbers are required operations in public key cryptography. Moreover, efficient execution of these two operations is important to achieve high performance levels in cryptographic engines and processes. The present invention uses multiplication and addition instead of using division and subtraction to perform modular arithmetic. The present invention also achieves some of its advantages through processing which begins with the high order bits coupled with judicious observations pertaining to circumstances under which carry output signals from addition operations are generated. These carry output signals are used to provide corrections which thus enable the use of the higher order bits and the efficiencies that such use engenders. Additionally, unlike other methods, the present invention avoids the baggage of preprocessing and post processing operations.Type: ApplicationFiled: October 2, 2002Publication date: April 8, 2004Applicant: International Business Machines CorporationInventor: Chin-Long Chen
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Publication number: 20040039767Abstract: To check hardware logic, one can duplicate the logic and compare the results from identical circuits. One can also use a check sum technique that predicts the check sum for the expected result and compare it against the check sum of the actual result produced by the hardware circuits. The present invention employs this technique for hardware which performs modular reduction operations which compute (A mod N) which is the calculation of the remainder of A divided by N, which can be expressed as B=N−AQ for some quotient Q. When R is the integer used as the modulus for the check sum, the check sum approach predicts the check sum of the remainder, that is, the check sum of (N−AQ) mod R. If C(x)=x mod R is the check sum of x, the predicted check sum is C(N−AQ)=(C(N)−C(A)C(Q)) mod R. Thus, a multiplier is normally required to calculate the predicted check sum.Type: ApplicationFiled: August 21, 2002Publication date: February 26, 2004Applicant: International Business Machines CorporationInventors: Chin-Long Chen, Vincenzo Condorelli, Samir K. Patel
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Patent number: 6675349Abstract: Advantage is taken of the presence of ordinary parity check bits occurring in the data flow in a computer or other information-handling system to improve error correction capability while at the same time providing simpler decoding. More particularly, the encoding and decoding system, methods, and devices herein include the capability of separating error correction in data bits and in parity check bits. In this regard, it is noted that the present invention therefore provides an improved memory system in which the parity check bits do not have to be stripped off prior to storage of data into a memory system with error correction coding redundancy built in. Instead of these parity check bits being stripped off, they are incorporated into a generalized and generalizable error correction system which produces a significantly simple decoding and error correction structure.Type: GrantFiled: May 11, 2000Date of Patent: January 6, 2004Assignee: International Business Machines CorporationInventor: Chin-Long Chen
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Patent number: 6675341Abstract: An apparatus and method is provided for correcting data words resulting from a package fail within a memory array in which coded data is divided into a plurality of multi-bit packages of b bits each. The coded data comprises n-bit words with r error correcting code bits and n-r data bits. The invention is capable of correcting one package which has suffered at least one hard failure. The invention correcting exploits single error correcting (SEC)-and double error detecting (DED) codes, requiring no additional check bits, which give a syndrome when the data word has suffered an error coming from at least one error in a package.Type: GrantFiled: November 17, 1999Date of Patent: January 6, 2004Assignee: International Business Machines CorporationInventors: Chin-Long Chen, Douglas C. Bossen
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Publication number: 20030140300Abstract: A method of detecting double-symbol errors and correcting single-symbol errors in a data stream being transmitted in a computer system, e.g., from a memory array to a memory controller. The method includes decoding the data stream which was encoded using a logic circuit which had, as inputs, the data being sent and two address parity bits derived from the system address of the data. Data retrieved from the wrong address can be detected by this code. The logic circuit is described by a parity-check matrix for this (146,130) code comprising 128 data bits, 16 check bits, and 2 address parity bits. Although the symbol width of the code is four bits, the code can also be used effectively in memory systems where the memory chip width is eight bits.Type: ApplicationFiled: January 23, 2003Publication date: July 24, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chin-Long Chen, R. Brett Tremaine, Michael E. Wazlowski
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Publication number: 20030093450Abstract: Finite field elements from the field GF(2k) are represented as polynomials with binary valued coefficients. As such, multiplication in the field is defined modulo an irreducible polynomial of degree k−1. One of the multiplicands is treated in blocks of polynomials of degree n−1 so that the multiplier operates over T cycles where k=nT. If k is not a composite number to start with, higher order terms are added, so that multipliers are now constructable even when k is prime. Since n<k, the construction of the needed multiplier circuits are much simpler. Designers are now provided with an opportunity of easily trading off circuit speed for circuit complexity in an orderly and structured fashion.Type: ApplicationFiled: October 9, 2001Publication date: May 15, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Chin-Long Chen
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Publication number: 20030072618Abstract: A precaution hose is a hollow cylindrical body made of waterproof material with a length thereof being cut as the actual need. Two seal plates are attached to the two ends of the cylindrical body respectively. A valve is mounted to the cylindrical body. The seal plates are touched to the edges of a gap thereof tightly and the cylindrical body is filled with the liquid till being full completely so that a lower part of the cylindrical body can press against the floor due to an inner liquid pressure to keep the floodwater out.Type: ApplicationFiled: November 13, 2001Publication date: April 17, 2003Inventors: Fu Sung Tang, Chin Long Chen, Shao Chi Huang, Chien Ju Hung, Szu Jen Chiu
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Patent number: 6539513Abstract: A method for constructing a single ECC that incorporates two codes into one is presented. This single ECC configuration can be applied to a memory configured in 2-bit-per-chip or 4-bit-per-chip. A mode bit M is used to indicate one of the two memory configurations.Type: GrantFiled: October 13, 1999Date of Patent: March 25, 2003Assignee: International Business Machines CorporationInventor: Chin-Long Chen