Abstract: A layout pattern decomposition method includes following steps. A layout pattern is received. The layout pattern includes a plurality of features, and an edge-to-edge space is respectively defined in between two adjacent features. A sum of a width of the edge-to-edge space and a width of the feature on a left side of the edge-to-edge space and a sum of the width of the edge-to-edge space and a width of the feature on a right side of the edge-to-edge space are respectively calculated. The sums and a predetermined value are respectively compared. When any one of the sums is smaller than the predetermined value, the two features on the two sides of the edge-to-edge space are colored by a first color and alternatively a second color. The features including the first color are assigned to a first pattern and the features including the second color to a second pattern.

Abstract: A method of decomposing pattern layout for generating patterns on photomasks is disclosed. The method includes decomposing features of an integrated circuit layout into discrete patterns based on the relation between these features. The features include first features and second features. The first features are then classified into a first feature pattern and a second feature pattern, and the second features are classified into third, fourth, fifth and sixth feature patterns. The spacings of the second features in the fifth and sixth feature patterns are greater than a minimum exposure limits. Finally, the first feature pattern is outputted to a first photomask, the second feature pattern is outputted to a second photomask, the third and fifth feature patterns are outputted to a third photomask, and the fourth and sixth feature patterns are outputted to a fourth photomask.

Abstract: A method of forming trenches is provided. A first layer, a second layer and a third layer are formed on the substrate. A patterned third layer with a plurality of third trenches is formed. A spacer is formed on sidewalls of the third trenches, following by removing a portion of the patterned third layer between the third trenches. By using the spacer and the patterned third layer as a mask, a patterned second layer with a plurality of second trenches is formed. Next, the patterned third layer and the spacer are completely removed, and a block layer is formed on the patterned second layer, filling into the at least one second trench to separate said second trench into at least two parts. The first layer is patterned by using the patterned second layer and the block layer as a mask to form a patterned first layer with first trenches.

Abstract: A method of forming trenches is provided. A first layer, a second layer and a third layer are formed on the substrate. A patterned third layer with a plurality of third trenches is formed. A spacer is formed on sidewalls of the third trenches, following by removing a portion of the patterned third layer between the third trenches. By using the spacer and the patterned third layer as a mask, a patterned second layer with a plurality of second trenches is formed. Next, the patterned third layer and the spacer are completely removed, and a block layer is formed on the patterned second layer, filling into the at least one second trench to separate said second trench into at least two parts. The first layer is patterned by using the patterned second layer and the block layer as a mask to form a patterned first layer with first trenches.

Abstract: A method of decomposing pattern layout for generating patterns on photomasks is disclosed. The method includes decomposing features of an integrated circuit layout into discrete patterns based on the relation between these features. The features include first features and second features. The first features are then classified into a first feature pattern and a second feature pattern, and the second features are classified into third, fourth, fifth and sixth feature patterns. The spacings of the second features in the fifth and sixth feature patterns are greater than a minimum exposure limits. Finally, the first feature pattern is outputted to a first photomask, the second feature pattern is outputted to a second photomask, the third and fifth feature patterns are outputted to a third photomask, and the fourth and sixth feature patterns are outputted to a fourth photomask.

Abstract: An optical proximity correction (OPC) process is provided. The method comprising receiving a first pattern corresponding to a first structure of a semiconductor structure, and a second pattern corresponding to a second structure of said semiconductor structure. Next, a first OPC process is performed for the first pattern to obtain a revised first pattern, wherein the revised first pattern has a first shift regarding to the first pattern. A second OPC process is performed for the second pattern to obtain a revised second pattern, wherein the second OPC process comprises moving the second pattern according to the first shift.

Abstract: A method for generating a layout pattern includes following steps. A basic layout pattern including a plurality of first stripe patterns in a first cluster region is provided. Each first stripe pattern extends in a first direction, and the first stripe patterns have equal pitches in a second direction. A plurality of anchor bar patterns are generated. Each anchor bar pattern extends in the first direction, and the anchor bar patterns have equal pitches in the second direction. Edges of at least one of the anchor bar patterns in the second direction are aligned with edges of two adjacent first stripe patterns respectively. At least one of the anchor bar patterns overlaps a first space between two adjacent first stripe patterns. At least one first mandrel pattern is generated at the first space overlapped by the anchor bar pattern, and the first mandrel pattern is outputted to a photomask.

Abstract: An image processing device for processing an image signal is provided. The image processing device includes a circuit board, a slot and an image processing module. The slot, disposed on the circuit board, is to be plugged in by either a first connector corresponding to a first image interface format or a second connector corresponding to a second image interface format. The image processing module, disposed on the circuit board and coupled to the slot, detects the image signal inputted from either the first connector or the second connector to determine a target image interface format, and processes the image signal by an image processing method corresponding to the target image interface format.

Abstract: A layout pattern decomposition method includes following steps. A layout pattern is received. The layout pattern includes a plurality of features, and an edge-to-edge space is respectively defined in between two adjacent features. A sum of a width of the edge-to-edge space and a width of the feature on a left side of the edge-to-edge space and a sum of the width of the edge-to-edge space and a width of the feature on a right side of the edge-to-edge space are respectively calculated. The sums and a predetermined value are respectively compared. When any one of the sums is smaller than the predetermined value, the two features on the two sides of the edge-to-edge space are colored by a first color and alternatively a second color. The features including the first color are assigned to a first pattern and the features including the second color to a second pattern.

Abstract: A method of optical proximity correction executed by a computer system for modifying line patterns includes the following steps. First, providing an integrated circuit layout with parallel line patterns and interconnect patterns disposed corresponding to the parallel line patterns. Then, using the computer to modify the integrated circuit layout based on a position of the interconnect patterns so as to generate a convex portion and a concave portion respectively on two sides of each of the parallel line patterns. Portions of the line pattern in front of and behind the convex portion and the concave portion are straight lines and have an identical critical dimension.

Abstract: A method of correcting assist features includes the following steps. At first, a first layout pattern is received by a computer system, and the first layout pattern is split into a plurality of first regions. Subsequently, a plurality of assist features are added into the first layout pattern to form a second layout pattern, wherein at least one of the assist features neighboring any one of the edges of the first regions is defined as a selected pattern. Then, the second layout pattern is split into a plurality of second regions. Afterwards, a check step is performed on the second region including the selected pattern, and the second layout pattern is corrected to form a corrected second layout pattern.

Abstract: A method of optical proximity correction executed by a computer system and integrated circuit layout formed by the same, the step of optical proximity correction comprises: providing an integrated circuit layout with a plurality of parallel line patterns, wherein one side of at least one line pattern is provided with a convex portion; and modifying the integrated circuit layout by forming a concave portion corresponding to the convex portion at the other side of the line pattern.

Abstract: An image processing device for processing an image signal is provided. The image processing device includes a circuit board, a slot and an image processing module. The slot, disposed on the circuit board, is to be plugged in by either a first connector corresponding to a first image interface format or a second connector corresponding to a second image interface format. The image processing module, disposed on the circuit board and coupled to the slot, detects the image signal inputted from either the first connector or the second connector to determine a target image interface format, and processes the image signal by an image processing method corresponding to the target image interface format.

Abstract: A method of correcting assist features includes the following steps. At first, a first layout pattern is received by a computer system, and the first layout pattern is split into a plurality of first regions. Subsequently, a plurality of assist features are added into the first layout pattern to form a second layout pattern, wherein at least one of the assist features neighboring any one of the edges of the first regions is defined as a selected pattern. Then, the second layout pattern is split into a plurality of second regions. Afterwards, a check step is performed on the second region including the selected pattern, and the second layout pattern is corrected to form a corrected second layout pattern.

Abstract: A method of optical proximity correction executed by a computer system and integrated circuit layout formed by the same, the step of optical proximity correction comprises: providing an integrated circuit layout with a plurality of parallel line patterns, wherein one side of at least one line pattern is provided with a convex portion; and modifying the integrated circuit layout by forming a concave portion corresponding to the convex portion at the other side of the line pattern.

Abstract: An LED light module free of jumper wires has a substrate and multiple LED chips. The substrate has a positive side circuit, a negative side circuit, multiple first chip connection portions and multiple second connection portions. The first and second chip connection portions are respectively connected to the positive and negative side circuits, and are juxtaposedly and alternately arranged on the substrate so that a width between each first chip connection portion and a corresponding second chip connection portion is smaller than a width of each LED chip. Each LED chip can be directly mounted on corresponding first and second chip connection portions to electrically connect to the positive and negative side circuits. Accordingly, jumper wires for connecting the LED chips and the positive and negative side circuits can be removed to avoid broken jumper wires occurring when the LED light module is shipped or assembled.

Abstract: An LED area light module has a substrate and a circuit layer and a solder mask layer formed on the substrate. The solder mask layer partially covers the circuit layer for the partially exposed circuit layer to form multiple electrical contacts. An embankment wall is formed on the solder mask layer with a solder mask material for the electrical contacts to be located within the embankment wall. Multiple LED chips are mounted on the solder mask layer within the embankment wall and electrically connected to the electrical contacts. Optically-transmissive adhesive is filled and concentrated within the embankment wall and covers the LED chips by a tension force thereof, and forms an optically-transmissive adhesive layer after congealed. Accordingly, the LED area light module eliminates the use of thick frame made of metal or rubber and steps of manufacturing and mounting the frame to simplify the packaging processes.

Abstract: An LED light module free of jumper wires has a substrate and multiple LED chips. The substrate has a positive side circuit, a negative side circuit, multiple first chip connection portions and multiple second connection portions. The first and second chip connection portions are respectively connected to the positive and negative side circuits, and are juxtaposedly and alternately arranged on the substrate so that a width between each first chip connection portion and a corresponding second chip connection portion is smaller than a width of each LED chip. Each LED chip can be directly mounted on corresponding first and second chip connection portions to electrically connect to the positive and negative side circuits. Accordingly, jumper wires for connecting the LED chips and the positive and negative side circuits can be removed to avoid broken jumper wires occurring when the LED light module is shipped or assembled.

Abstract: A tubeless light-emitting diode (LED) based lighting device includes at least one base, at least one LED lighting module, and at least one control circuit. The base includes a heat dissipation body. The LED lighting module is mounted to the base so that the base provides the LED lighting module with the functions of retention and heat dissipation. The control circuit is mounted to the base and is electrically connected to power wiring of the LED lighting module for ON/OFF switching of the LED lighting module and supplying of operation power. As such, a tubeless lighting device that emits light in a power saving manner and is constructed in a volume reduced manner is provided.

Abstract: A multifunctional emergency lighting device includes at least one base formed of a heat sink, at least one LED lighting module, at least one emergency LED lighting module, a power control circuit, and at least one backup power supply device. The LED lighting module and the emergency LED lighting module are both mounted in the base. The power control circuit is connected to the LED lighting module and the emergency LED lighting module for converting AC to DC current for charging the backup power supply device and powers the LED lighting module and the emergency LED lighting module. In case of power failure of the electric main, the backup power supply device supplies electrical power to the power control circuit for powering the emergency LED lighting module in order to activate the emergency lighting of the emergency LED lighting module.