Abstract: A memory cell having a kinked polysilicon layer structure, or a polysilicon layer structure with a top portion being narrower than a bottom portion, may greatly reduce random single bit (RSB) failures and may improve high density plasma (HDP) oxide layer fill-in by reducing defects caused by various impurities and/or a polysilicon layer short path. A kinked polysilicon layer structure may also be applied to floating gate memory cells either at the floating gate structure or the control gate structure.

Abstract: A system is provided that includes a power supply connectable to a semiconductor wafer including opposing, major front and back surfaces joined by a circumferential side, with the wafer undergoing processing including electroplating a damascene layer on the wafer. The system also includes an arrangement configured to apply a polymer coating to the side of the wafer before electroplating the damascene layer, with the system being configured to apply the polymer coating in accordance with an electrophoresis technique driven by the power supply. In this regard, the polymer coating is applied to the side but not at least a portion of the front and back surfaces of the wafer, and the polymer coating provides a barrier to formation of the damascene layer on the side of the wafer.

Abstract: A polysilicon structure and method of forming the polysilicon structure are disclosed, where the method includes a two-step deposition and planarization process. The disclosed process reduces the likelihood of defects such as voids, particularly where polysilicon is deposited in a trench having a high aspect ratio. A first polysilicon structure is deposited that includes a trench liner portion and a first upper portion. The trench liner portion only partially fills the trench, while the first upper portion extends over the adjacent field isolation structures. Next, at least a portion of the first upper portion of the first polysilicon structure is removed. A second polysilicon structure is then deposited that includes a trench plug portion and a second upper portion. The trench is filled by the plug portion, while the second upper portion extends over the adjacent field isolation structures. The second upper portion is then removed.

Abstract: A conductor removal process is described, which is applied to a substrate that has thereon a plurality of patterns and a blanket conductor layer covering the patterns. An upper portion of the blanket conductor layer entirely over the patterns is oxidized to form a dielectric layer. A CMP step is performed to remove the dielectric layer and a portion of the remaining conductor layer in turn and thereby expose the patterns.

Abstract: An advance process control (APC) system for a plasma process machine is provided, which includes at least an optical emission spectroscopy (OES) system and an APC analysis apparatus. The OES system is used for monitoring a testing object in the plasma process machine. The APC analysis apparatus is used for analyzing the data received from the OES system.

Abstract: Techniques for forming metal silicide contact pads on semiconductor devices are disclosed, and in one exemplary embodiment, a method may comprise depositing a metal layer on and between a plurality of raised silicon-based features formed on a semiconductor substrate, the metal layer comprising metal capable of reacting with external silicon-based portions of the features to form a metal silicide. In addition, such a method may also include depositing a cap layer on the metal layer deposited on and between the plurality of raised silicon-based features, wherein a thickness of the cap layer on the metal layer between the raised features is greater than or equal to a thickness of the cap layer on the metal layer on the raised features. Furthermore, such a method may also include annealing the structure to cause portions of the metal layer to react with portions of the external silicon-based portions of the features to form metal silicide pads on and between the raised features.

Abstract: A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the dielectric material; (d) removing the dielectric material over the base by performing a chemical mechanical polishing (CMP) process until a part of the stop layer is exposed so as to form a dielectric layer in the recess; and (e) removing a part of the stop layer, wherein the another part of the stop layer and the dielectric layer filled in the recess constitute the isolation structure.

Abstract: Methods for fabricating conductive metal lines of a semiconductor device are described herein. In one embodiment, such a method may comprise depositing a conductive material over a substrate, and depositing a first barrier layer on the conductive layer. Such a method may also comprise patterning a mask on the first barrier layer, the pattern comprising a layout of the conductive lines. Such an exemplary method may also comprise etching the conductive material and the first barrier layer using the patterned mask to form the conductive lines. In addition, a low temperature post-flow may be performed on the structure. The method may also include depositing a dielectric material over and between the patterned conductive lines.

Abstract: A method for chemical-mechanical polishing two adjacent structures of a semiconductor device is provided. The method for mechanical polishing comprising: (a) providing a semiconductor device comprising a recess formed in a surface thereof, a first layer formed over the surface, and a second layer filled with the recess and formed on the first layer; and (b) substantially polishing the first and second layer with a pad and a substantially inhibitor-free slurry, wherein the pad comprising a corrosion inhibitor of the second layer.

Abstract: An HDP-CVD system is described, including an HDP-CVD chamber for depositing a material on a wafer, and a pre-heating chamber disposed outside of the HDP-CVD chamber to pre-heat the wafer, before the wafer is loaded in the HDP-CVD chamber, to a temperature higher than room temperature and required in the deposition step to be conducted in the HDP-CVD chamber. The pre-heating chamber is equipped with a heating lamp for the pre-heating. The wafer has been formed with a trench before being pre-heated.

Abstract: An advance process control (APC) system for a plasma process machine is provided, which includes at least an optical emission spectroscopy (OES) system and an APC analysis apparatus. The OES system is used for monitoring a testing object in the plasma process machine. The APC analysis apparatus is used for analyzing the data received from the OES system.

Abstract: A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the dielectric material; (d) removing the dielectric material over the base by performing a chemical mechanical polishing (CMP) process until a part of the stop layer is exposed so as to form a dielectric layer in the recess; and (e) removing a part of the stop layer, wherein the another part of the stop layer and the dielectric layer filled in the recess constitute the isolation structure.

Abstract: A chemical mechanical polishing method includes employing a topologically selective slurry or an abrasive trapped or abrasive mounted pad in an initial polishing operation to provide a substantially planar topology of a polysilicon layer of a semiconductor wafer, and performing a second polishing operation to remove a portion of the polysilicon layer to expose discrete elements of the semiconductor wafer.

Abstract: A method for chemical-mechanical polishing two adjacent structures of a semiconductor device is provided. The method for mechanical polishing comprising: (a) providing a semiconductor device comprising a recess formed in a surface thereof, a first layer formed over the surface, and a second layer filled with the recess and formed on the first layer; and (b) substantially polishing the first and second layer with a pad and a substantially inhibitor-free slurry, wherein the pad comprising a corrosion inhibitor of the second layer.

Abstract: An HDP-CVD process is described, including a deposition step conducted in an HDP-CVD chamber and a pre-heating step that is performed outside of the HDP-CVD chamber before the deposition step and pre-heats a wafer to a temperature higher than room temperature and required in the HDP-CVD process deposition step.

Abstract: A method for depositing a barrier layer onto a substrate is disclosed. A layer of titanium (Ti) is deposited onto the substrate using an ionized metal plasma (IMP) physical vapor deposition process. The IMP process includes: generating gaseous ions, accelerating the gaseous ions towards a titanium target, sputtering the titanium atoms from the titanium target with the gaseous ions, ionizing the titanium atoms using a plasma, and depositing the ionized titanium atoms onto the substrate to form the layer of Ti. A first layer of titanium nitride (TiN) is deposited onto the layer of Ti using a metal organic chemical vapor deposition (MOCVD) process. A second layer of TiN is deposited onto the first layer of TiN using a thermal chemical vapor deposition process. The newly completed barrier layer is annealed in the presence of nitrogen at a temperature of between about 500° C. to about 750° C.

Abstract: A method for depositing a barrier layer onto a substrate is disclosed. A layer of titanium (Ti) is deposited onto the substrate using an ionized metal plasma (IMP) physical vapor deposition process. The IMP process includes: generating gaseous ions, accelerating the gaseous ions towards a titanium target, sputtering the titanium atoms from the titanium target with the gaseous ions, ionizing the titanium atoms using a plasma, and depositing the ionized titanium atoms onto the substrate to form the layer of Ti. A first layer of titanium nitride (TiN) is deposited onto the layer of Ti using a metal organic chemical vapor deposition (MOCVD) process. A second layer of TiN is deposited onto the first layer of TiN using a thermal chemical vapor deposition process. The newly completed barrier layer is annealed in the presence of nitrogen at a temperature of between about 500° C. to about 750° C.

Abstract: A method of a fabricating a semiconductor device includes providing a substrate having a first region and a second region. A pad layer is formed overlying the substrate in both the first region and the second region. A mask layer is then formed overlying the pad layer. Thereafter, the mask layer, the pad layer and the substrate are patterned to form a plurality of first trenches in the first region and a plurality of second trenches in the second region. A trimming process is then performed on the mask layer to remove a portion of the mask layer. An insulation layer is formed over the substrate and fills the plurality of the first trenches and the plurality of the second trenches. Ultimately, a planarization process is performed on the insulation layer.

Abstract: A metal pad formation method and metal pad structure using the same are provided. A wider first pad metal is formed together with a first metal. A dielectric layer is then deposited thereon. A first opening and a second opening are formed in the dielectric layer to respectively expose the first metal and the first pad metal. Then, the first opening is filled by W metal to generate a first via. Finally, a second metal and a second pad metal are formed to respectively cover the first via and the first pad metal to generate the metal pad.

Abstract: A method of forming a non-volatile memory cell is provided. The method comprises: (a) providing a substrate; (b) forming a stacking structure on the substrate, the stacking structure at least comprising an oxide-nitride-oxide layer (ONO layer) and a polysilicon layer thereon; (c) patterning the stacking structure to form a plurality of separated stacking units, each two stacking units having an aperture therebetween; (d) forming a source region and a drain region buried in the substrate at two sides of the each stacking unit; (e) forming an oxide layer in the aperture and over the stacking units; and (f) performing a chemical mechanical polishing (CMP) process to remove the oxide layer over the stacking units and outside the aperture.