Abstract: This invention provides a method for forming a microcrystalline polysilicon layer by using silane or dislane with introducing hydrogen gas. This microcrystalline polysilicon layer can be used as a floating gate of a flash memory to improve the character of the flash memory.

Abstract: A method is provided for forming a semiconductor device that reduces metal-stress-induced photo misalignment by incorporating a multi-layered anti-reflective coating over a metal layer. The method includes providing a substrate with a conductive layer formed over the substrate, depositing a multi-layered anti-reflective coating (including alternating layers of titanium and titanium nitride), defining a plurality of conductive lines in connection with a first etching step, depositing a dielectric layer, and defining at least one via in connection with a second etching step.

Abstract: A method for forming a shallow trench isolation region (STI) is disclosed. The method comprises the steps of sequentially forming a pad oxide layer and a nitride silicon layer over a provided substrate. Next, the pad oxide layer, the nitride silicon layer, and the substrate are partially etched to form a trench. An oxide liner and a nitride liner are then formed in the trench. Subsequently, a two-stage high-density plasma chemical vapor deposition process is performed to form a shallow trench isolation region.

Abstract: A high density plasma chemical vapor deposition (HDPCVD) process is disclosed. First, a first deposition step is performed on a wafer. Then, the wafer is rotated with an angle. A second deposition step is performed for completing the deposition. By the rotation of the wafer, the thin film is formed with a desired uniformity.

Abstract: Integrated circuits and methods of making an integrated circuit are disclosed. The disclosed methods include providing a substrate having at least one device structure thereon; providing a first barrier layer over the substrate and the at least one device structure; providing a dielectric layer formed by a spin-on-glass process; and providing a second barrier layer over the dielectric layer, wherein the second barrier layer is a compressive layer. Integrated circuits described herein include a first barrier layer over the substrate and the at least one device structure; a dielectric layer formed by a spin-on-glass process; and a second barrier layer over the dielectric layer, wherein the second barrier layer is a compressive layer.

Abstract: Methods and apparatuses are disclosed relating to blocking ultraviolet electromagnetic radiation from a semiconductor. Ultraviolet electromagnetic radiation, such as ultraviolet electromagnetic radiation generated by a plasma process, which may otherwise damage a semiconductor can be blocked from one or more layers below an ultraviolet blocking layer.

Abstract: A method for forming a semiconductor device includes providing a substrate, providing aluminum metal lines on the substrate, forming a barrier layer over the aluminum metal lines, and forming a silicon-rich dielectric layer over the barrier layer. An inter-metal dielectric (IMD) layer may be formed to cover at least a portion of the silicon-rich dielectric layer.

Abstract: A method for controlling the properties of a dielectric anti-reflective coating (DARC) is provided. In the process of forming the DARC, a nitrogen-containing gas is added to a reaction gas comprising silicon-containing gas and oxygen for controlling the n value of the DARC. Furthermore, the proportion of the silicon-containing gas to the oxygen or the proportion of the silicon-containing gas to the nitrogen-containing gas is increased to control the k value of the DARC. By means of proper control of the n value and the k value, the DARC can have the lowest substrate reflectivity.

Abstract: A method for forming a memory device includes providing a substrate, providing a plurality of features on the substrate, and forming a silicon-rich dielectric layer over the features. An inter-layer dielectric (ILD) or inter-metal dielectric (IMD) layer may be formed by a spin-on-glass (SOG) process on the silicon-rich dielectric layer, the silicon-rich dielectric layer preventing diffusion of a solvent used in the SOG process.

Abstract: This invention provides a method for forming polysilicon by using silane with introducing hydrogen, such that polysilicon is microcrystalline. This microcrystal polysilicon can be applied to floating gate of flash memory to improve the character of flash memory.

Abstract: A semiconductor process is described. On a dielectric layer, a planarization process is performed and then a material layer is formed. Next, an opening is formed in the material layer and the dielectric layer. In a subsequent thermal process, the material layer is converted into a material layer with compressive stress so as to prevent defect from forming in the dielectric layer. A method of fabricating an inter-layer dielectric is also described. A dielectric layer is first formed on a substrate, and a planarization process is then performed on the dielectric layer. A material layer is subsequently formed on the dielectric layer. After a thermal process, the material layer is converted into a material layer with compressive stress. Therefore, formation of cracks in the dielectric layer can be prevented, and device reliability and yield can be increased.

Abstract: A method for controlling the properties of a dielectric anti-reflective coating (DARC) is provided. In the process of forming the DARC, a nitrogen-containing gas is added to a reaction gas comprising silicon-containing gas and oxygen for controlling the n value of the DARC. Furthermore, the proportion of the silicon-containing gas to the oxygen or the proportion of the silicon-containing gas to the nitrogen-containing gas is increased to control the k value of the DARC. By means of proper control of the n value and the k value, the DARC can have the lowest substrate reflectivity.

Abstract: A method is provided for forming a semiconductor device that reduces metal-stress-induced photo misalignment by incorporating a multi-layered anti-reflective coating over a metal layer. The method includes providing a substrate with a conductive layer formed over the substrate, depositing a multi-layered anti-reflective coating (including alternating layers of titanium and titanium nitride), defining a plurality of conductive lines in connection with a first etching step, depositing a dielectric layer, and defining at least one via in connection with a second etching step.

Abstract: A high density plasma chemical vapor deposition (HDPCVD) process is disclosed. First, a first deposition step is performed on a wafer. Then, the wafer is rotated with an angle. A second deposition step is performed for completing the deposition. By the rotation of the wafer, the thin film is formed with a desired uniformity.

Abstract: Methods and apparatuses are disclosed relating to blocking ultraviolet electromagnetic radiation from a semiconductor. Ultraviolet electromagnetic radiation, such as ultraviolet electromagnetic radiation generated by a plasma process, which may otherwise damage a semiconductor can be blocked from one or more layers below an ultraviolet blocking layer.

Abstract: A method of improving thermal stability for cobalt salicide includes providing a substrate which has a silicon layer formed thereon. A cobalt layer is formed over the silicon layer, and TiNx layer is formed over the cobalt layer. The TiNx layer includes x atoms of nitrogen for each atom of titanium in a TiNx molecule, and a value of x is greater than 0.9. A first thermal process is then performed to form a cobalt salicide layer over the silicon layer. Any non-reactive cobalt is removed, and a second thermal process is performed to enhance the conductivity of the cobalt salicide layer.

Abstract: A method of filling intervals between protruding structures is provided. A substrate with a plurality of protruding structures thereon is provided. The protruding structures are distributed over the substrate such that intervals are formed between adjacent protruding structures. A first dielectric layer is formed over the substrate so that the dielectric material fills the intervals between the protruding structures and covers the protruding structures as well. The first dielectric layer has a plurality of apertures therein located at a level above a top section of the protruding structures. A chemical/mechanical polishing operation is performed to remove a portion of the dielectric layer and expose the apertures to form a plurality of openings. An anisotropic etching operation is performed to increase the width of these openings. Finally, a second dielectric layer is formed over the first dielectric layer to fill the openings completely.

Abstract: A single chip pad oxide layer growth process is disclosed. First, a silicon chip is sent into a reaction chamber, which is filled with hydrogen and oxygen. A rapid thermal process is employed to increase the temperature inside the chamber to about 850° C. to 1100° C. to grow a SiO2 layer. The error on the final temperature after the rapid thermal process can be controlled to fluctuate within one to two degrees.

Abstract: This invention provides a method for forming polysilicon by using silane with introducing hydrogen, such that polysilicon is microcrystalline. This microcrystal polysilicon can be applied to floating gate of flash memory to improve the character of flash memory.

Abstract: A single chip pad oxide layer growth process is disclosed. First, a silicon chip is sent into a reaction chamber, which is filled with hydrogen and oxygen. A rapid thermal process is employed to increase the temperature inside the chamber to about 850° C. to 1100° C. to grow a SiO2 layer. The error on the final temperature after the rapid thermal process can be controlled to fluctuate within one to two degrees.