Patents by Inventor Chin-Tien Chiu

Chin-Tien Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11302673
    Abstract: A semiconductor device is disclosed including one or more stacks of semiconductor dies vertically molded together in an encapsulated block. The semiconductor dies may comprise memory dies, or memory dies and a controller die.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: April 12, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Xuyi Yang, Cong Zhang, Chin-Tien Chiu
  • Patent number: 11276669
    Abstract: A semiconductor device is disclosed including wafers of stacked integrated memory modules. A semiconductor device of the present technology may include multiple memory array semiconductor wafers, and a CMOS controller wafer, which together, operate as a single, integrated flash memory semiconductor device. In embodiments, the CMOS controller wafer may include semiconductor dies comprising ASIC logic circuits integrated together with memory array logic circuits.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: March 15, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Xuyi Yang, Shineng Ma, Cong Zhang, Chin-Tien Chiu
  • Patent number: 11257785
    Abstract: A semiconductor device is disclosed including a multi-module interposer for enabling communication between one or more semiconductor dies within the device and a host device on which the semiconductor device is mounted. The multi-module interposer may be formed at the wafer level, and provides fan-out signal paths to and from the one or more dies in the device. Additionally, the multi-module interposer allows any of a variety of different semiconductor packaging configurations to be formed at the wafer level, including for example wire bonded packages, flip chip packages and through silicon via (TSV) packages.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: February 22, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Cong Zhang, Chin-Tien Chiu, Xuyi Yang, Yazhou Zhang
  • Publication number: 20220052002
    Abstract: Systems, methods, and devices for 3D packaging. In some embodiments, a semiconductor package includes a first die and a second die. The first die includes a first bonding pad on a top of the first die and near a first edge of the first die. The second die includes a second bonding pad on a top of the second die and near a second edge of the second die. A pillar is located on the second bonding pad. The first die is mounted on top of the second die such that the first edge is parallel to the second edge and offset from the second edge such that the pillar is exposed. A wire is bonded to a bonding surface of the pillar and bonded to a bonding surface of the first bonding pad.
    Type: Application
    Filed: October 29, 2021
    Publication date: February 17, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Xuyi Yang, Fuqiang Xiao, Cong Zhang, Kuo-Chien Wang, Chin-Tien Chiu
  • Publication number: 20210400811
    Abstract: A memory card includes a memory card body dimensioned to house at least one integrated circuit die package. The memory card body, in certain embodiments, includes a first surface spaced apart from a second surface and a plurality of side surfaces connecting the first surface to the second surface. The memory card also includes a contact pad disposed on at least one side surface of the plurality of side surfaces. The contact pad includes a first conductive layer, a second conductive layer, and an insulating layer disposed between the first conductive layer and the second conductive layer.
    Type: Application
    Filed: November 30, 2020
    Publication date: December 23, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: SHINENG MA, XUYI YANG, CHIH-CHIN LIAO, CHIN-TIEN CHIU, JINXIANG HUANG
  • Patent number: 11189582
    Abstract: Systems, methods, and devices for 3D packaging. In some embodiments, a semiconductor package includes a first die and a second die. The first die includes a first bonding pad on a top of the first die and near a first edge of the first die. The second die includes a second bonding pad on a top of the second die and near a second edge of the second die. A pillar is located on the second bonding pad. The first die is mounted on top of the second die such that the first edge is parallel to the second edge and offset from the second edge such that the pillar is exposed. A wire is bonded to a bonding surface of the pillar and bonded to a bonding surface of the first bonding pad.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: November 30, 2021
    Assignee: Western Digital Technologies Inc.
    Inventors: Xuyi Yang, Fuqiang Xiao, Cong Zhang, Kuo-Chien Wang, Chin-Tien Chiu
  • Publication number: 20210366875
    Abstract: A semiconductor device includes a vertical column of wire bonds on substrate contact fingers of the device. Semiconductor dies are mounted on a substrate, and electrically coupled to the substrate such that groups of semiconductor dies may have bond wires extending to the same contact finger on the substrate. By bonding those wires to the contact finger in a vertical column, as opposed to separate, side-by-side wire bonds on the contact finger, an area of the contact finger may be reduced.
    Type: Application
    Filed: December 30, 2020
    Publication date: November 25, 2021
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Xiaofeng Di, Junrong Yan, CheeKeong Chin, Weili Wang, Xin Lu, Qi Deng, Chaur Yang Ng, Cong Zhang, Chenlin Yang, Chin-Tien Chiu
  • Patent number: 11177239
    Abstract: A semiconductor device including control switches enabling a semiconductor die in a stack of semiconductor die to send or receive a signal, while electrically isolating the remaining die in the die stack. Parasitic pin cap is reduced or avoided by electrically isolating the non-enabled semiconductor die in the die stack.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: November 16, 2021
    Assignee: SanDisk Information Technology (Shanghai) Co., Ltd.
    Inventors: Shineng Ma, Chin-Tien Chiu, Chih-Chin Liao, Ye Bai, Yazhou Zhang, Yanwen Bai, Yangming Liu
  • Patent number: 11031372
    Abstract: A semiconductor device is disclosed including a stack of semiconductor die on a substrate, wherein a semiconductor die in the stack is wire bonded to the substrate using dummy wire bonds. Each dummy wire bond has a stiffness so that together, the dummy wire bonds effectively pull and/or hold down the die stack against the substrate.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: June 8, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Han-Shiao Chen, Chih-Chin Liao, Chin-Tien Chiu
  • Patent number: 11031371
    Abstract: The present technology relates to a semiconductor package. The semiconductor package comprises: a first component comprising a plurality of first dies stacked on top of each other, each of first dies comprising at least one side surface and an electrical contact exposed on the side surface, and the plurality of first dies aligned so that the corresponding side surfaces of all first dies substantially coplanar with respect to each other to form a common sidewall; a first conductive pattern formed over the sidewall and at least partially spaced away from the sidewall, the first conductive pattern electrically interconnecting the electrical contacts of the plurality of first dies; at least one second component; and a second conductive pattern formed on a surface of the second component, the second conductive pattern affixed and electrically connected to the first conductive pattern formed over the sidewall of the first component.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: June 8, 2021
    Assignee: SanDisk Information Technology (Shanghai) Co., Ltd.
    Inventors: Chin Tien Chiu, Tiger Tai, Ken Qian, C C Liao, Hem Takiar, Gursharan Singh
  • Patent number: 11031378
    Abstract: A semiconductor device is disclosed including a controller die and a memory module. The controller die may be a heterogeneous integrated controller die having ASIC logic circuits, memory array logic circuits and a cache structure. In examples, the memory module may have continuously formed through silicon vias in a face-up or face-down configuration.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: June 8, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yazhou Zhang, Chin-Tien Chiu, Zengyu Zhou
  • Publication number: 20210151399
    Abstract: Systems, methods, and devices for 3D packaging. In some embodiments, a semiconductor package includes a first die and a second die. The first die includes a first bonding pad on a top of the first die and near a first edge of the first die. The second die includes a second bonding pad on a top of the second die and near a second edge of the second die. A pillar is located on the second bonding pad. The first die is mounted on top of the second die such that the first edge is parallel to the second edge and offset from the second edge such that the pillar is exposed. A wire is bonded to a bonding surface of the pillar and bonded to a bonding surface of the first bonding pad.
    Type: Application
    Filed: December 6, 2019
    Publication date: May 20, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Xuyi Yang, Fuqiang Xiao, Cong Zhang, Kuo-Chien Wang, Chin-Tien Chiu
  • Publication number: 20210043602
    Abstract: A substrate-less integrated electronic element module for a semiconductor package, comprising: at least two electronic elements, each of the at least two electronic elements having first electrical connectors; and a first molding compound encapsulating the at least two electronic elements, the first molding compound comprising a first planar surface and an opposing second planar surface of the integrated electronic element module, wherein each of the first electrical connectors is directly exposed on the first planar surface of the integrated electronic element module. Further, a semiconductor package including the integrated electronic element module and the method of fabricating the same is provided.
    Type: Application
    Filed: May 29, 2020
    Publication date: February 11, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Cong Zhang, Chin-Tien Chiu, Xuyi Yang, Qi Deng
  • Publication number: 20200411480
    Abstract: A semiconductor device is disclosed including wafers of stacked integrated memory modules. A semiconductor device of the present technology may include multiple memory array semiconductor wafers, and a CMOS controller wafer, which together, operate as a single, integrated flash memory semiconductor device. In embodiments, the CMOS controller wafer may include semiconductor dies comprising ASIC logic circuits integrated together with memory array logic circuits.
    Type: Application
    Filed: March 13, 2020
    Publication date: December 31, 2020
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Xuyi Yang, Shineng Ma, Cong Zhang, Chin-Tien Chiu
  • Publication number: 20200411496
    Abstract: A semiconductor die is provided. The semiconductor die includes: at least one complementary metal oxide semiconductor (CMOS) circuit module electrically coupled to at least one memory die, the at least one memory die being separated from the semiconductor die; and a controller module electrically coupled to the CMOS circuit module and configured to control the at least one CMOS circuit module and the at least one memory die. A semiconductor package is also provided.
    Type: Application
    Filed: March 13, 2020
    Publication date: December 31, 2020
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yazhou Zhang, Chin-Tien Chiu, Shineng Ma
  • Publication number: 20200411481
    Abstract: A semiconductor device is disclosed including one or more stacks of semiconductor dies vertically molded together in an encapsulated block. The semiconductor dies may comprise memory dies, or memory dies and a controller die.
    Type: Application
    Filed: March 13, 2020
    Publication date: December 31, 2020
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Xuyi Yang, Cong Zhang, Chin-Tien Chiu
  • Publication number: 20200411479
    Abstract: A semiconductor device is disclosed including a controller die and a memory module. The controller die may be a heterogeneous integrated controller die having ASIC logic circuits, memory array logic circuits and a cache structure. In examples, the memory module may have continuously formed through silicon vias in a face-up or face-down configuration.
    Type: Application
    Filed: March 13, 2020
    Publication date: December 31, 2020
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yazhou Zhang, Chin-Tien Chiu, Zengyu Zhou
  • Patent number: 10872856
    Abstract: A semiconductor device is disclosed including a stack of semiconductor die. Openings are formed in the semiconductor die as they are added to the stack, which openings are aligned at different levels of the stack. The openings are filled with an electrically insulative compound to form a molded column through all semiconductor die in the stack. After all semiconductor die are added to the stack, a via may be drilled through the molded column to electrically interconnect each semiconductor die in the stack.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: December 22, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yazhou Zhang, Chin-Tien Chiu, Cong Zhang
  • Publication number: 20200365554
    Abstract: A semiconductor device is disclosed including a multi-module interposer for enabling communication between one or more semiconductor dies within the device and a host device on which the semiconductor device is mounted. The multi-module interposer may be formed at the wafer level, and provides fan-out signal paths to and from the one or more dies in the device. Additionally, the multi-module interposer allows any of a variety of different semiconductor packaging configurations to be formed at the wafer level, including for example wire bonded packages, flip chip packages and through silicon via (TSV) packages.
    Type: Application
    Filed: March 13, 2020
    Publication date: November 19, 2020
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Cong Zhang, Chin-Tien Chiu, Xuyi Yang, Yazhou Zhang
  • Patent number: 10818575
    Abstract: A solid state drive is disclosed including a planar array of semiconductor devices for use in a datacenter, and a system for cooling the planar array of semiconductor devices. The semiconductor devices may be arranged in a grid pattern, spaced apart from each other so as to define rows and columns of flow pathways, or cooling tunnels, around and between the semiconductor devices.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: October 27, 2020
    Assignee: SanDisk Information Technology (Shanghai) Co., Ltd.
    Inventors: Chin-Tien Chiu, Zhongli Ji, Hem Takiar