Abstract: A checkerboard deep trench dynamic random access memory cell array layout is disclosed, which includes a substrate, a plurality of gate conductor lines disposed on the substrate, a plurality of checkerboard-arranged and staggered deep trench capacitor structures embedded in the substrate under the gate conductor lines, and a plurality of active areas formed in the substrate under the gate conductor lines, alternatively arranged with the deep trench capacitor structures, and electrically connected with an adjacent deep trench capacitor structure. The width of the parts of the gate conductor lines above the deep trench capacitor structures is narrower than that of the parts of the gate conductor lines above the active areas.

Abstract: A holographic data storage medium and a fabrication method thereof are provided. First, a precursor solution including an ultraviolet curable adhesive composition including a monomer having at least one (meth)acryloyl group in the molecule and an oligomer having at least two (meth)acryloyl groups in the molecule, a photopolymerizable organic compound and a photoinitiator including 2, 4, 6 trimethyl benzoldiphenyl phosphine oxide is provided. Next, a first substrate and a second substrate are attached to one another such that a gap is formed between the first and second glass substrates. Next, the precursor solution is filled into the gap. Next, the precursor solution between the first and second substrates is irradiated with a light in an atmosphere of an inert gas to induce photo-polymerization reaction to form the recording layer.

Abstract: A method for fabricating a disc stamper is provided. First, a substrate is provided. Next, a layer of a coatable inorganic material is coated on the substrate, wherein the coatable inorganic material is an oxide, in which the chemical element constitution is more than one element selected from the group consisting of Te, Al, Zr, and Ti. Next, a laser beam is utilized to perform direct write on the layer of the coatable inorganic material to form a relief pattern. Thereafter, a metal layer is electroplated on the relief pattern. Next, the metal layer is separated from the relief pattern. The layer of the coatable inorganic material is utilized to form the relief pattern, so that it is more compatibility to equipment apparatus and lower cost in contrast with sputtered PTM process.

Abstract: A coatable inorganic material is provided, which is suitable for being coated on a substrate in the form of sol-gel solution and then being directly written with thermochemical mode by using a laser beam. The coatable inorganic material is an oxide, in which the chemical element constitution is more than one element selected from Te, Al, Zr, and Ti.

Abstract: A method for forming a semiconductor device is disclosed, in which a substrate comprising a recessed gate is provided, and a protrusion of the recessed gate protrudes a surface of the substrate. A spacer is formed on a sidewall of the protrusion of the recessed gate. A conductive structure is formed overlying the recessed gate, wherein the conductive structure is narrower than the recessed gate to expose a portion of the recessed gate. An etching process is utilized to recess a exposed portion of the recessed gate, and form a recess portion between the recessed gate and the spacer. A conductive line spacer is formed on a sidewall of the conductive line structure, wherein the conductive line spacer fills the recessed portion.

Abstract: A video camera apparatus for whole space monitoring is provided, which includes a lens module having a plurality of lenses, a calculation unit, and a processing unit. The lens module captures images from different directions and generates a plurality of image data, then outputs the image data to the calculation unit. The calculation unit calculates the received image data and outputs the image data to the processing unit. The processing unit compresses the image data according to the output of the calculation unit and outputs the compressed image data to the host apparatus.

Abstract: A method of videophone data transmission based on the PKI (Public Key Infrastructure) is executed with a videophone and a user. The method includes the steps of performing a connection procedure, performing a data download procedure and performing a disconnection procedure. While performing the connection procedure, a smart key, which stores at least one piece of user identification data, is connected to a videophone. The user identification data contains an ID code, a password and a private key of the user. While performing the data download procedure, the user identification data is encrypted and transmitted to a service server for verifying the user. Then, at least one service provided by the service server is encrypted and downloaded to the videophone. After decryption, the at least one service can be executed in the videophone. While performing a disconnection procedure, the smart key is disconnected from the videophone.

Abstract: A method of videophone data transmission based on the PKI (Public Key Infrastructure) is executed with a videophone and a user. The method includes the steps of performing a connection procedure, performing a data download procedure and performing a disconnection procedure. While performing the connection procedure, a smart key, which stores at least one piece of user identification data, is connected to a videophone. The user identification data contains an ID code, a password and a private key of the user. While performing the data download procedure, the user identification data is encrypted and transmitted to a service server for verifying the user. Then, at least one service provided by the service server is encrypted and downloaded to the videophone. After decryption, the at least one service can be executed in the videophone. While performing a disconnection procedure, the smart key is disconnected from the videophone.

Abstract: A method for manufacturing a dual damascene structure, which forms a trench first, is described. The manufacturing method has following steps. First, a substrate with a plurality of semiconductor devices is provided. A first metal layer, a first etching stop layer, a dielectric layer, and a second etching stop layer are subsequently formed thereon. A trench is formed in the dielectric layer at a predetermined depth thereafter, and a sacrificial layer is filled therein and is next planarized. Then a photoresist layer is formed thereon for etching a via. Afterward the photoresist layer and the sacrificial layer are both removed. Following that, the first etching stop layer is etched through to expose the first metal layer. Finally, the via and the trench are filled with a second metal layer.

Abstract: A method for manufacturing a dual damascene structure, which forms a trench first, is described. The manufacturing method has following steps. First, a substrate with a plurality of semiconductor devices is provided. A first metal layer, a first etching stop layer, a dielectric layer, and a second etching stop layer are subsequently formed thereon. A trench is formed in the dielectric layer at a predetermined depth thereafter, and a sacrificial layer is filled therein and is next planarized. Then a photoresist layer is formed thereon for etching a via. Afterward the photoresist layer and the sacrificial layer are both removed. Following that, the first etching stop layer is etched through to expose the first metal layer. Finally, the via and the trench are filled with a second metal layer.

Abstract: An integrated circuit chip is provided, which includes a bond pad structure, a low-k dielectric layer, and active circuits. The bond pad structure includes a conductive bond pad, an Mtop solid conductive plate, and an Mtop?1 solid conductive plate. The Mtop solid conductive plate is located under the bond pad. The Mtop plate is electrically coupled to the bond pad. The Mtop?1 solid conductive plate is located under the Mtop plate. A low-k dielectric layer is located under the bond pad of the bond pad structure. At least part of an active circuit is located under the bond pad of the bond pad structure.

Abstract: A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.

Abstract: A method for manufacturing a dual damascene structure, which forms a trench first, is described. The manufacturing method has following steps. First, a substrate with a plurality of semiconductor devices is provided. A first metal layer, a first etching stop layer, a dielectric layer, and a second etching stop layer are subsequently formed thereon. A trench is formed in the dielectric layer at a predetermined depth thereafter, and a sacrificial layer is filled therein and is next planarized. Then a photoresist layer is formed thereon for etching a via. Afterward the photoresist layer and the sacrificial layer are both removed. Following that, the first etching stop layer is etched through to expose the first metal layer. Finally, the via and the trench are filled with a second metal layer.

Abstract: A dual bit ROM multilayered structure with improved write and erase functions and a method of manufacturing is disclosed. The structure includes a pair of floating gates at the middle or nitride layer to better define the two locations of electrons representing the dual data bits collected in the middle layer.

Abstract: A method of fabricating an interconnect structure, including providing a semiconductor substrate having a first conductive layer thereon, and forming a dielectric layer overlying the semiconductor substrate and the first conductive layer. An opening is formed in the dielectric layer extending to the first conductive layer. A portion of the first conductive layer is removed through the opening to form a recess having a substantially curvilinear profile. The opening and the recess are filled with a second conductive layer.

Abstract: A dual bit ROM multilayered structure with improved write and erase functions and a method of manufacturing is disclosed. The structure includes a pair of floating gates at the middle or nitride layer to better define the two locations of electrons representing the dual data bits collected in the middle layer.

Abstract: A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.

Abstract: A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.

Abstract: A method of reducing or substantially eliminating the number of tungsten plug pullouts and consequential chip failures by controlling the CMP step of removing the overfilled tungsten so as to leave a thin layer of tungsten instead of continuing the removal down to the top surface of the dielectric layer.

Abstract: A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.