Abstract: A magnetism characteristic detection method, a magnetism characteristic detection apparatus, an imaging apparatus and an imaging method are provided, where magnetism detection and imaging are based on an integrated excitation field of a direct current (DC) magnetic field and an oscillation wave. The magnetism detection method includes the following steps. A DC magnetic field is selectively applied to an object. Further, an oscillation wave is provided to the object, where the oscillation wave is a sound wave or an ultrasound wave. Then, a magnetism characteristic variation of the object is detected.

Abstract: A display device and a manufacturing method thereof are provided. The display device includes a first substrate, a second substrate, a drive IC and a protection layer. The first substrate has a first region and a second region. The second substrate is correspondingly disposed on the first region. The drive IC is disposed on the second region. The protection layer is disposed enclosing the drive IC, and the protection layer has a maximum height larger than the height of the drive IC.

Abstract: A system and method for efficient allocation of remote storage devices to computing devices in a rack is disclosed. An end of the rack switch is provided with physical storage devices and a storage service. The switch includes ports that are coupled to network interface cards of computing servers. The storage service allows each of the computing servers to access the physical storage devices. The network interface card includes a controller that can be configured into virtual storage controllers to allow access to different storage volumes.

Abstract: The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectively depositing a diffusion barrier layer on the metal. In the method, selectively depositing the diffusion barrier layer includes pre-treating the surface of the metal; disposing a precursor to selectively form a partially-decomposed precursor layer on the metal; and exposing the partially-decomposed precursor layer to a plasma to form the diffusion barrier layer. The method further includes forming an MTJ structure on the interconnect layer over the diffusion barrier layer, where the bottom electrode of the MTJ structure is aligned to the diffusion barrier layer.

Abstract: A structure is provided that includes a first conductive component and a first interlayer dielectric (ILD) that surrounds the first conductive component. A self-assembly layer is formed on the first conductive component but not on the first ILD. A first dielectric layer is formed over the first ILD but not over the first conductive component. A second ILD is formed over the first conductive component and over the first ILD. An opening is etched in the second ILD. The opening is at least partially aligned with the first conductive component. The first dielectric layer protects portions of the first ILD located therebelow from being etched. The opening is filled with a conductive material to form a second conductive component in the opening.

Abstract: The present disclosure relates generally to systems and methods that may reduce a reduction in visual artifacts related to hysteresis of a light emitting diode (LED) electronic display. In one example, an electronic device may include a controller. The controller is may provide a signal to a pixel of a display of the electronic device while at least a portion of the display is turned off. The signal may include a first current and a second current. The first current may be designed to increase an ambient temperature corresponding to the pixel. The second current may be generated as part of an active panel conditioning operation. By applying the first current and the second current, hysteresis settling times from the pixel may improve, therefore improving speeds of sensing and compensation operations of the electronic device.

Abstract: A photo mask for manufacturing a semiconductor device includes a first pattern extending in a first direction, a second pattern extending in the first direction and aligned with the first pattern, and a sub-resolution pattern extending in the first direction, disposed between an end of the first pattern and an end of the second pattern. A width of the first pattern and a width of the second pattern are equal to each other, and the first pattern and the second pattern are for separate circuit elements in the semiconductor device.

Abstract: A display device including a backlight module is provided. The backlight module includes: a substrate, a backlight cavity, a plurality of light emitting elements, and an optical adjustment layer. The backlight cavity is located on the substrate. The plurality of light emitting elements is disposed in the backlight cavity. The optical adjustment layer covers the plurality of light emitting elements and fills the remaining space of the backlight cavity. The optical adjustment layer has a refractive index n greater than the refractive index n0 of the air.

Abstract: A semiconductor device is disclosed including a stack of semiconductor die. Openings are formed in the semiconductor die as they are added to the stack, which openings are aligned at different levels of the stack. The openings are filled with an electrically insulative compound to form a molded column through all semiconductor die in the stack. After all semiconductor die are added to the stack, a via may be drilled through the molded column to electrically interconnect each semiconductor die in the stack.

Abstract: A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming an etch stop layer over a semiconductor substrate and forming a magnetic element over the etch stop layer. The method also includes forming an isolation element extending across the magnetic element. The isolation element partially covers the top surface of the magnetic element and partially covers sidewall surfaces of the magnetic element. The method further includes forming a conductive line over the isolation element. In addition, the method includes forming a dielectric layer over the conductive line, the isolation element, and the magnetic element.

Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method for integrated circuit (IC) fabrication includes forming a passivation layer over a first contact feature, forming a second contact feature over and through the passivation layer to electrically connect to the first contact feature, and forming a multi-layer passivation structure over the second contact feature and over the passivation layer. Forming the multi-layer passivation structure includes depositing a first nitride layer, an oxide layer over the first nitride layer, and a second nitride layer over the oxide layer.

Abstract: A hydrogen gas generating system that heats a liquid reactant such as water, then channeling the resultant heated reactant to a reaction chamber containing a solid hydride. The chemical reaction between the heated liquid reactant and solid hydride forming hydrogen gas. This hydrogen gas is then filtered and regulated before being stored in a buffer tank. Hydrogen gas from the buffer tank can then be supplied to a fuel cell to produce electricity as and when needed, such as when a battery goes below a predetermined level. The pressure of the buffer tank is measured and used to ascertain when the hydrogen gas generation should start and stop. A pressure and temperature of the reaction chamber is measured as a safety precaution, whereby the reaction will be stopped if the pressure and temperature exceeds predetermined values.

Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.

Abstract: A magnetic iron alloy and process of making the same. The alloy includes iron, approximately 2 wt. % to approximately 8 wt. % cobalt, approximately 0.05 wt. % to approximately 5 wt. % manganese, and approximately 0.05 wt. % to approximately 5 wt. % silicon. The alloy may also include up to approximately 0.3 wt. % chromium, up to approximately 2 wt. % vanadium, up to approximately 1 wt. % nickel, up to approximately 0.05 wt. % niobium, and up to approximately 0.02 wt. % carbon.

Abstract: A molded semiconductor package includes a mold compound having opposing first and second main surfaces and an edge extending between the first and second main surfaces. A semiconductor die is embedded in the mold compound. A plurality of metal pads embedded in the mold compound are electrically connected to the semiconductor die. The metal pads have a bottom face which is uncovered by the mold compound at the second main surface of the mold compound. The metal pads disposed around a periphery of the molded package have a side face which is uncovered by the mold compound at the edge of the mold compound. The faces of the metal pads uncovered by the mold compound are plated. The side face of each metal pad disposed around the periphery of the molded package is recessed inward from the edge of the mold compound. A corresponding manufacturing method is also described.

Abstract: Certain aspects of the present disclosure provide techniques for selecting policies for routing of data traffic. Certain aspects provide a method for wireless communication by a user-equipment (UE). The method generally includes selecting at least one policy for routing of data traffic to a network, wherein the policy comprise an access network discovery and selection policy (ANDSP) if the UE has the ANDSP provisioned regardless of whether the UE is registered to evolved packet core (EPC) or fifth-generation core network (5GCN), and communicating the data traffic to the network based on the selection.

Abstract: A hinge structure and a casing using the same are provided. The hinge structure includes a first component and a second component. The first component includes a shaft and a connection member, wherein the shaft is fixed on the connection member. The second component includes a bushing and a limiting member, wherein the shaft is received in the bushing, the limiting member is disposed on the bushing, and the first component is detachably installed on the second component through the limiting member.

Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.

Abstract: A method for electroless metal deposition and an electroless metal layer included substrate are provided. The method for electroless metal deposition includes steps as follows. a) cleaning a substrate, applying a hydrofluoric acid onto the substrate; and then applying a modifying agent onto the substrate to form a chemical oxide layer on the substrate; b) a catalyst layer is formed on the chemical oxide layer, wherein, the catalyst layer includes a plurality of colloidal nanoparticles, and each of the plurality of colloidal nanoparticles includes a palladium nanoparticle and a polymer which encapsulates the palladium nanoparticle, and c) depositing a metal on the catalyst layer through an electroless metal deposition to form an electroless metal layer.