Abstract: Provided is a method for treating cancer by administering to a subject in need thereof with a pharmaceutical composition including a benzenesulfonamide derivative in combination with a cancer immunotherapeutic agent such as the immune check point inhibitor (ICI).

Abstract: A detection circuit is provided herein, which includes a first transistor, a second transistor, a third transistor, a light sensor, a capacitor, and a fourth transistor. The first transistor has a control terminal, a first terminal, and a second terminal. The second transistor is coupled to the control terminal. The third transistor is coupled to the control terminal and the second terminal. The light sensor is coupled to the control terminal. The capacitor is coupled to the control terminal. The fourth transistor is coupled to the second terminal.

Abstract: Provided is a pharmaceutical composition for treating malignant peripheral nerve sheath (MPNST), including a benzenesulfonamide derivative and a pharmaceutically acceptable carrier. Also provided is a method for treating canine MPNST by administering the pharmaceutical composition to a subject in need thereof.

Abstract: A structure of capacitors connected in parallel includes a substrate. A trench embedded in the substrate. Numerous electrode layers respectively conformally fill in and cover the trench. The electrode layers are formed of numerous nth electrode layers, wherein n is a positive integer from 1 to M, and M is not less than 3. The nth electrode layer with smaller n is closer to the sidewall of the trench. When n equals to M, the Mth electrode layer fills in the center of the trench, and the top surface of the Mth electrode is aligned with the top surface of the substrate. A capacitor dielectric layer is disposed between the adjacent electrode layers. A first conductive plug contacts the nth electrode layer with odd-numbered n. A second conductive plug contacts the nth electrode layer with even-numbered n.

Abstract: A semiconductor structure includes a semiconductor on insulator (SOI) substrate, a first electrically conductive structure, and a second electrically conductive structure. The SOI substrate includes a base substrate, a buried insulation layer disposed on the base substrate, a semiconductor layer disposed on the buried insulation layer, and a trap rich layer disposed between the buried insulation layer and the base substrate. At least a part of the first electrically conductive structure and at least a part of the second electrically conductive structure are disposed in the trap rich layer. A part of the trap rich layer is disposed between the first electrically conductive structure and the second electrically conductive structure. The first electrically conductive structure, the second electrically conductive structure, and the trap rich layer disposed between the first electrically conductive structure and the second electrically conductive structure are at least a portion of an anti-fuse structure.

Abstract: A sensing device is provided. The sensing device includes a substrate, a circuit layer, a photosensitive element, a light-shielding layer, and a conductive layer. The circuit layer is disposed on the substrate. The photosensitive element is disposed on the substrate and is electrically connected to the circuit layer. The light-shielding layer is disposed on the photosensitive element and has an opening. The opening overlaps the photosensitive element. The conductive layer is disposed on the light-shielding layer. In addition, the conductive layer passes through the opening and is electrically connected to the photosensitive element. A method of manufacturing a sensing device is also provided.

Abstract: A method of forming a protective layer utilized in a silicon remove process includes bonding a first wafer to a second wafer, wherein the first wafer comprises a first silicon substrate with a first device structure disposed thereon and the second wafer comprises a second silicon substrate with a second device structure disposed thereon. After that, a first trim process is performed to thin laterally an edge of the first wafer and an edge of the second device structure. After the first trim process, a protective layer is formed to cover a back side of the second silicon substrate. After forming the protective layer, a silicon remove process is performed to remove only the first silicon substrate.

Abstract: A semiconductor device includes a substrate, a high-Q capacitor, an ultra high density capacitor, and an interconnection. At least one trench is formed in the substrate. The high-Q capacitor is disposed on a surface of the substrate, and includes a bottom electrode, an upper electrode located on the bottom electrode, and a first dielectric layer located between the upper and bottom electrodes. The ultra high density capacitor is disposed on the trench of the substrate, and includes a first electrode conformally deposited in the trench, a second electrode located on the first electrode, and a second dielectric layer located between the first and second electrodes. The interconnection connects one of the upper electrode and the bottom electrode to one of the first electrode and the second electrode, and connects the other of the upper electrode and the bottom electrode to the other of the first electrode and the second electrode.

Abstract: A method of fabricating a semiconductor device is provided. First, a semiconductor structure is provided, and the semiconductor structure includes a buried dielectric layer, a first gate structure disposed on a front-side of the buried dielectric layer, and a first source/drain region and a second source/drain region disposed between the buried dielectric layer and the first gate structure. Then, a trench is formed in the buried dielectric layer. Afterwards, a conductive layer is formed on the buried dielectric layer and in the trench. Finally, the conductive layer is patterned.

Abstract: An electronic device includes a first transistor, a second transistor, and a sensing circuit coupled to at least one of the first transistor and the second transistor. The sensing circuit includes a diode, a third transistor, and a fourth transistor. The diode has a first terminal. The third transistor has a first terminal and a second terminal. The first terminal of the third transistor is coupled to the first terminal of the diode. The fourth transistor has a first terminal coupled to the second terminal of the third transistor, and a second terminal coupled to a data driver.

Abstract: A composite optical film comprises: a first substrate; a plurality of reversed prisms disposed on a bottom surface of the first substrate; and a first diffusion film disposed over a top surface of the first substrate.

Abstract: A microbial inhibition device for inhibiting microorganisms on a predetermined object includes: a covering member covering the predetermined object, and having an attachment surface for attaching to the predetermined object, and an exposed surface opposite to the attachment surface, wherein the covering member includes at least a conductive medium layer, and the conductive medium layer constitutes a predetermined area of the exposed surface; a control module configured to issue a control command reflecting a predetermined conduction mode; and a power supply module electrically connected to the conductive medium layer, and configured to receive the control command so as to power the conductive medium layer according to the predetermined conduction mode based on the control command. The conductive medium layer is conducted with current according to the predetermined conduction mode through the power supply module. Accordingly predetermined microorganisms on the predetermined area are inhibited or killed.

Abstract: A reflective sheet comprises a plurality of perforations for extending a plurality of light-emitting elements therein, the reflective sheet further comprises a central line passing through its center, at least one first dimming area, and at least one second dimming area, and the distance between the at least one first dimming area and the central line is smaller than the distance between the at least one second dimming area and the central line. The light-emitting elements are distributed in the at least one first dimming area and the at least one second dimming area, the at least one first dimming area has a first dimming means, the at least one second dimming area has a second dimming means, the dimension of the first dimming means is different from the dimension of the second dimming means.

Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain

Abstract: Provided is a method for treating cancer by administering to a subject in need thereof with a pharmaceutical composition including a benzenesulfonamide derivative and at least one other therapeutic agents in a different classification of anticancer agents.

Abstract: A card device and a manufacturing method thereof are disclosed. The card device includes a first substrate, a circuit board, a sensing module and a second substrate. The circuit board is disposed on the first substrate, and the circuit board includes an accommodating recess. The sensing module is disposed in the accommodating recess. The sensing module includes a sensing unit and a protective layer formed on the sensing unit, and the sensing unit is electrically connected to the circuit board. The second substrate is disposed on the circuit board. The second substrate includes an opening, and the opening exposes the protective layer.

Abstract: A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.

Abstract: An insulation resistance detection circuit is coupled to a positive end and a negative end of a DC power source, and is used to detect a positive insulation resistance between the positive end and a ground point and detect a negative insulation resistance between the negative end and the ground point. A detection unit sets a first estimated resistance and a second estimated resistance, and acquires a first voltage based on turning on the switch and acquires a second voltage based on turning off the switch. The detection unit calculates a third voltage and a fourth voltage according to the first estimated resistance and the second estimated resistance so as to detect the positive insulation resistance and the negative insulation resistance when the third voltage is equal to the first voltage and the fourth voltage is equal to the second voltage.

Abstract: A sensing device, including a plurality of sensing pixels arranged in Y rows and M columns, a plurality of readout lines coupled to the sensing pixels, and a plurality of control lines each coupled to a sensing pixel subset, is provided. The Y times N sensing pixels within the sensing pixel subset are arranged in adjacent N columns, where Y, M and N are integers and N is smaller than M. Each of the control lines is configured to control one row of the sensing pixel subset to output signals through corresponding readout lines.

Abstract: The invention provides a method for dynamically adjusting user interface, an electronic device and a computer-readable storage medium. The method includes: displaying a user interface, wherein the user interface partially displays a first block, and the first block includes at least one layer; monitoring a first moving direction of a first specific object; in response to determining that the first specific object moves toward the first block, moving at least one of the at least one layer in the first block toward a reference point in the user interface.