Abstract: A method of producing an epitaxial semiconductor wafer includes measuring one or more epitaxial semiconductor wafers to determine an epitaxial deposition layer profile produced by an epitaxy apparatus. The method also includes polishing a semiconductor wafer using a polishing assembly and measuring the polished semiconductor wafer to determine a surface profile of the polished wafer. The method further includes generating a predicted post-epitaxy surface profile of the polished wafer by comparing the surface profile of the polished wafer and the determined epitaxial deposition layer profile produced by the epitaxy apparatus. The method also includes determining a predicted post-epitaxy parameter based on the predicted post-epitaxy surface profile and adjusting, based on the predicted post-epitaxy parameter, a process condition of the polishing assembly.

Abstract: A semiconductor structure includes a glass substrate and a device structure. The glass substrate includes a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate. Or, the glass substrate includes a glass layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer, and a heat dissipation layer is stacked on the device layer, wherein the heat dissipation layer is bonded with the silicon nitride layer of the glass substrate. The present invention also provides a method of wafer bonding for manufacturing said semiconductor structure.

Abstract: An electronic device is provided. The electronic device includes a substrate, a first conductive layer disposed on the substrate, a planarization layer disposed on the first conductive layer, an electric element, and a second conductive layer disposed on the planarization layer. The first conductive layer and the second conductive layer include an output line and a control line, respectively. The electric element is used to produce a first signal. The electronic device further includes a switching element, which is used to receive the first signal and output the first signal to the output line according to a second signal of the control line. The output line and the control line partially overlap.

Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain

Abstract: A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.

Abstract: A radiofrequency device includes a buried insulation layer, a transistor, a contact structure, a connection bump, an interlayer dielectric layer, and a mold compound layer. The buried insulation layer has a first side and a second side opposite to the first side in a thickness direction of the buried insulation layer. The transistor is disposed on the first side of the buried insulation layer. The contact structure penetrates the buried insulation layer and is electrically connected with the transistor. The connection bump is disposed on the second side of the buried insulation layer and electrically connected with the contact structure. The interlayer dielectric layer is disposed on the first side of the buried insulation layer and covers the transistor. The mold compound layer is disposed on the interlayer dielectric layer. The mold compound layer may be used to improve operation performance and reduce manufacturing cost of the radiofrequency device.

Abstract: A detection apparatus for unbalanced DC link capacitor voltage, the DC link provides a DC voltage and includes a plurality of capacitors coupled in series to two ends of the DC link and a plurality of balanced resistors coupled in series to two ends of the DC link and corresponding to the capacitors. The detection apparatus includes a plurality of sense resistors and a current sensor. One end of each sense resistor is coupled to a common-connected node of two capacitors, and the other end thereof is coupled to a common-connected node of two balanced resistors. The current sensor is coupled to one of the sense resistors and measures a current value of a current flowing through the sense resistor coupled to the current sensor.

Abstract: An electronic device includes a first transistor, a second transistor, and a sensing circuit coupled to at least one of the first transistor and the second transistor. The sensing circuit includes a diode, a third transistor, and a fourth transistor. The diode has a first terminal. The third transistor has a first terminal and a second terminal. The first terminal of the third transistor is coupled to the first terminal of the diode. The fourth transistor has a first terminal coupled to the second terminal of the third transistor, and a second terminal coupled to a data driver.

Abstract: A composite optical film comprises a first optical film and a second optical film disposed on the first optical film, wherein the first optical film comprises a first substrate; a plurality of reversed prisms disposed on a bottom surface of the first substrate; and a first diffusion film disposed over a top surface of the first substrate; and the second optical film comprises a first PET film thereon having a first set of prisms and a second PET film having a second set of prisms thereon, wherein the first PET film and the second PET film are laminated together.

Abstract: A detection circuit is provided herein, which includes a first transistor, a second transistor, a third transistor, a light sensor, a capacitor, and a fourth transistor. The first transistor has a control terminal, a first terminal, and a second terminal. The second transistor is coupled to the control terminal. The third transistor is coupled to the control terminal and the second terminal. The light sensor is coupled to the control terminal. The capacitor is coupled to the control terminal. The fourth transistor is coupled to the second terminal.

Abstract: A polishing head assembly for polishing of semiconductor wafers includes a polishing head and a cap. The polishing head has a recess along a bottom portion. The recess has a recessed surface. The cap is positioned within the recess. The cap includes an annular wall secured to the polishing head and a floor joined to the annular wall at a joint. The floor extends across the annular wall, and the floor has an upper surface and a lower surface. The upper surface is spaced from the recessed surface to form a chamber therebetween. A deformation resistance of a portion of the floor proximate the joint is weakened to allow the portion of the floor proximate the joint to deflect relative to the polishing head by a change of pressure in the chamber.

Abstract: An additive manufacturing (AM) method includes using an AM tool to fabricate a plurality of workpiece products; measuring qualities of the first workpiece products respectively; performing a temperature measurement on each of the melt pools on the powder bed during a fabrication of each of the workpiece products; performing photography on each of the melt pools on the powder bed during the fabrication of each of the workpiece products; extracting a length and a width of each of the melt pools; performing a melt-pool feature processing operation; building a conjecture model by using a plurality of sets of first process data and the actual metrology values of the first workpiece products in accordance with a prediction algorithm; and predicting a virtual metrology value of the second workpiece product by using the conjecture model based on a set of second process data.

Abstract: An additive manufacturing (AM) method includes using an AM tool to fabricate a plurality of workpiece products; measuring qualities of the first workpiece products respectively; performing a temperature measurement on each of the melt pools on the powder bed; performing photography on each of the melt pools on the powder bed; extracting a length and a width of each of the melt pools; performing a melt-pool feature processing operation; first converting each of the workspace images to a gray level co-occurrence matrix (GLCM); building a conjecture model by using a plurality of sets of first process data and the actual metrology values of the first workpiece products in accordance with a prediction algorithm; and predicting a virtual metrology value of the second workpiece product by using the conjecture model based on a set of second process data.

Abstract: A sensing device includes a sensing circuit, a conductive line, and a sampling circuit. The conductive line is electrically connected to the sensing circuit. The sampling circuit is electrically connected to the conductive line. The sampling circuit includes a capacitor, a first thin film transistor, and a second thin film transistor. The first terminal of the first thin film transistor is electrically connected to the first terminal of the capacitor. The first terminal of the second thin film transistor is electrically connected to the second terminal of the capacitor. The second terminal of the first thin film transistor is electrically connected to the conductive line. The second terminal of the second thin film transistor is electrically connected to the ground terminal.

Abstract: A sensing device is provided herein, which operates in a reset period, an exposure period, and a readout period. The sensing device includes a first transistor, a second transistor, a detection device, and a third transistor. The first transistor includes a control terminal and a first terminal. The second transistor is coupled to the first transistor and configured to set the voltage of the control terminal during the exposure period. The sensing device is coupled to the first transistor and configured to change the voltage of the control terminal during the exposure period. The third transistor is coupled to the first transistor and includes an output terminal outputting a sense signal from the first terminal during the readout period. The first transistor is an N-type transistor and the third transistor is a P-type transistor.

Abstract: A semiconductor structure includes a glass substrate and a device wafer. The glass substrate includes a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top. The device wafer includes at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate. Or, the glass substrate includes a glass layer and a silicon nitride layer stacked from bottom to top. The device wafer includes at least one semiconductor device integrated in a device layer, and a heat dissipation layer is stacked on the device layer, wherein the heat dissipation layer is bonded with the silicon nitride layer of the glass substrate. The present invention also provides a method of wafer bonding for manufacturing said semiconductor structure.

Abstract: An optical film, comprising a substrate, wherein a first plurality of multi-faceted recesses are formed on the substrate, wherein the plurality of multi-faceted recesses are capable of scattering lights that enter into a second surface of the substrate, said first surface and said second surface are two opposite surfaces of the substrate.

Abstract: A composite optical film, comprising: a quantum-dot film and a first optical film disposed over the quantum-dot film, wherein a first plurality of multi-faceted recesses are formed on a first surface of the first optical film, wherein each multi-faceted recess comprises a shape of a reversed cone.

Abstract: An electronic device includes a reset circuit and a first image sensing circuit. The reset circuit is used to receive a reset signal and includes a plurality of transistors. The first image sensing circuit is coupled to the reset circuit and includes a photodiode, a first transistor and a second transistor. The photodiode has a first terminal. The first transistor has a first terminal coupled to the first terminal of the photodiode, and a second terminal. The second transistor has a first terminal coupled to the second terminal of the first transistor, and a second terminal configured to receive a row selection signal.

Abstract: A reflective sheet comprises a plurality of perforations for extending a plurality of light-emitting elements therein, the reflective sheet further comprises a central line passing through its center, at least one first dimming area, and at least one second dimming area, and the distance between the at least one first dimming area and the central line is smaller than the distance between the at least one second dimming area and the central line. The light-emitting elements are distributed in the at least one first dimming area and the at least one second dimming area, the at least one first dimming area has a first dimming means, the at least one second dimming area has a second dimming means, the dimension of the first dimming means is different from the dimension of the second dimming means.