Patents by Inventor Ching-Chih Li
Ching-Chih Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11940828Abstract: A voltage tracking circuit is provided. The voltage tracking circuit includes first and second P-type transistors and a control circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The gate and the drain of the second P-type transistor are respectively coupled to the first voltage terminal and a second voltage terminal. The control circuit is coupled to the first and second voltage terminals and generates a control voltage according to the first voltage and the second voltage. The sources of the first and second P-type transistors are coupled to an output terminal of the voltage tracking circuit, and the output voltage is generated at the output terminal. In response to the second voltage being higher than the first voltage, the control circuit generates the control signal to turn off the first P-type transistor.Type: GrantFiled: August 17, 2022Date of Patent: March 26, 2024Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Shao-Chang Huang, Yeh-Ning Jou, Ching-Ho Li, Kai-Chieh Hsu, Chun-Chih Chen, Chien-Wei Wang, Gong-Kai Lin, Li-Fan Chen
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Publication number: 20230125573Abstract: The present invention provides a device for testing a chip, wherein the device includes a testing board and an interposer. The testing board has a plurality of pads for providing a plurality of test signals. The interposer board includes a plurality of passive components, and at least one of the passive components is coupled between a supply voltage and a ground voltage, and the supply voltage and the ground voltage are received from a power pad and a ground pad of the plurality of pads of the testing board, respectively; wherein the chip is positioned in the device, the chip receives the test signals including the supply voltage and the ground voltage from the power pad and the ground pad of the testing board, respectively.Type: ApplicationFiled: December 23, 2022Publication date: April 27, 2023Applicant: MEDIATEK INC.Inventors: Ching-Chih Li, Sheng-Ming Chang
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Patent number: 11573264Abstract: The present invention provides a device for testing a chip, wherein the device includes a testing board and an interposer. The testing board has a plurality of pads for providing a plurality of test signals. The interposer board includes a plurality of passive components, and at least one of the passive components is coupled between a supply voltage and a ground voltage, and the supply voltage and the ground voltage are received from a power pad and a ground pad of the plurality of pads of the testing board, respectively; wherein the chip is positioned in the device, the chip receives the test signals including the supply voltage and the ground voltage from the power pad and the ground pad of the testing board, respectively.Type: GrantFiled: March 24, 2020Date of Patent: February 7, 2023Assignee: MEDIATEK INC.Inventors: Ching-Chih Li, Sheng-Ming Chang
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Publication number: 20200326368Abstract: The present invention provides a device for testing a chip, wherein the device includes a testing board and an interposer. The testing board has a plurality of pads for providing a plurality of test signals. The interposer board includes a plurality of passive components, and at least one of the passive components is coupled between a supply voltage and a ground voltage, and the supply voltage and the ground voltage are received from a power pad and a ground pad of the plurality of pads of the testing board, respectively; wherein the chip is positioned in the device, the chip receives the test signals including the supply voltage and the ground voltage from the power pad and the ground pad of the testing board, respectively.Type: ApplicationFiled: March 24, 2020Publication date: October 15, 2020Inventors: Ching-Chih Li, Sheng-Ming Chang
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Patent number: 10581414Abstract: A semiconductor integrated circuit device includes a chip main circuit, a damper and a passive component. The chip main circuit is coupled to a power source and performs a predetermined function. The damper is coupled to an output terminal of the chip main circuit. The passive component is coupled to the chip main circuit via the damper.Type: GrantFiled: September 23, 2016Date of Patent: March 3, 2020Assignee: MediaTek Inc.Inventors: Chun-Neng Liao, Meng-Hsin Chiang, Chun-Wei Chang, Chee-Kong Ung, Ching-Chih Li
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Patent number: 9978692Abstract: An integrated circuit is provided. The integrated circuit includes a control circuitry, a plurality of pins, and a plurality of driving units coupled to the pins. The control circuitry provides a plurality of control signals according to data to be transmitted. The pins are coupled to a device via a plurality of conductive traces of a printed circuit board (PCB). The control signals control each of the driving units to selectively provide the data or one specific shielding pattern via the corresponding pin and the corresponding conductive trace of PCB to the device.Type: GrantFiled: January 15, 2016Date of Patent: May 22, 2018Assignee: MediaTek Inc.Inventors: PoHao Chang, Chun-Wei Chang, Ching-Chih Li
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Patent number: 9846756Abstract: A layout method for a printed circuit board (PCB) is provided. The method obtains a memory type of a dynamic random access memory (DRAM) to be mounted on the PCB, obtains a module group from a database according to the memory type of the DRAM, wherein the module group comprises a plurality of routing modules, obtains a plurality of PCB parameters, selects a specific routing module from the module group according to the PCB parameters, and implements the specific routing module into a layout design for PCB fabrication. The specific routing module comprises layout information regarding a main chip, a memory chip and a routing configuration between the main chip and the memory chip.Type: GrantFiled: September 2, 2015Date of Patent: December 19, 2017Assignee: MEDIATEK INCInventors: Fu-Kang Pan, Nan-Cheng Chen, Shih-Chieh Lin, Hui-Chi Tang, Ying Liu, Yang Liu, Ching-Chih Li
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Publication number: 20170111032Abstract: A semiconductor integrated circuit device includes a chip main circuit, a damper and a passive component. The chip main circuit is coupled to a power source and performs a predetermined function. The damper is coupled to an output terminal of the chip main circuit. The passive component is coupled to the chip main circuit via the damper.Type: ApplicationFiled: September 23, 2016Publication date: April 20, 2017Inventors: Chun-Neng LIAO, Meng-Hsin CHIANG, Chun-Wei CHANG, Chee-Kong UNG, Ching-Chih LI
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Publication number: 20160233174Abstract: An integrated circuit is provided. The integrated circuit includes a control circuitry, a plurality of pins, and a plurality of driving units coupled to the pins. The control circuitry provides a plurality of control signals according to data to be transmitted. The pins are coupled to a device via a plurality of conductive traces of a printed circuit board (PCB). The control signals control each of the driving units to selectively provide the data or one specific shielding pattern via the corresponding pin and the corresponding conductive trace of PCB to the device.Type: ApplicationFiled: January 15, 2016Publication date: August 11, 2016Inventors: PoHao CHANG, Chun-Wei CHANG, Ching-Chih LI
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Publication number: 20160218092Abstract: A chip package includes a first die encapsulated by a molding compound; a board comprising a chip mounting surface; a redistributed layer (RDL) structure on an active surface of the first die and between the die and the chip mounting surface; and a discrete passive device embedded in the molding compound and situated in close proximity to a side edge of the first die.Type: ApplicationFiled: October 23, 2015Publication date: July 28, 2016Inventors: Po-Hao Chang, Chun-Wei Chang, Ching-Chih Li
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Publication number: 20150379180Abstract: A layout method for a printed circuit board (PCB) is provided. The method obtains a memory type of a dynamic random access memory (DRAM) to be mounted on the PCB, obtains a module group from a database according to the memory type of the DRAM, wherein the module group comprises a plurality of routing modules, obtains a plurality of PCB parameters, selects a specific routing module from the module group according to the PCB parameters, and implements the specific routing module into a layout design for PCB fabrication. The specific routing module comprises layout information regarding a main chip, a memory chip and a routing configuration between the main chip and the memory chip.Type: ApplicationFiled: September 2, 2015Publication date: December 31, 2015Inventors: Fu-Kang PAN, Nan-Cheng CHEN, Shih-Chieh LIN, HUI-CHI TANG, Ying LIU, Yang LIU, Ching-Chih Li
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Publication number: 20150379184Abstract: A printed circuit board (PCB) is provided. The PCB has a specific routing module, having a first chip, a memory chip, and a plurality of traces designed for interconnection between the first chip and the memory chip according to a routing configuration between the first chip and the memory chip. The memory chip is a dynamic random access memory (DRAM) with a memory type, the specific routing module is obtained from a module group comprising a plurality of routing modules according to a plurality of PCB parameters, and module group is obtained from a database according to the memory type of the DRAM.Type: ApplicationFiled: September 2, 2015Publication date: December 31, 2015Inventors: Fu-Kang PAN, Nan-Cheng CHEN, Shih-Chieh LIN, HUI-CHI TANG, Ying LIU, Yang LIU, Ching-Chih Li
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Patent number: 8525310Abstract: A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads disposed along peripheral edges of the die pad; a ground bar between the leads and the die pad; and a plurality of bridges connecting the ground bar with the die pad, wherein a gap between two adjacent bridges has a length that is equal to or less than 3 mm.Type: GrantFiled: April 12, 2011Date of Patent: September 3, 2013Assignee: Mediatek Inc.Inventors: Nan-Jang Chen, Chun-Wei Chang, Sheng-Ming Chang, Che-Yuan Jao, Ching-Chih Li, Nan-Cheng Chen
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Patent number: 8283757Abstract: An electronic package is provided. The electronic package comprises a die pad having a die attached thereon. A plurality of leads surrounds the die pad and spaced therefrom to define a ring gap therebetween. At least one first common electrode bar is in the ring gap and substantially coplanar to the die pad, in which at least one of the plurality of leads extends to the first common electrode bar. A molding compound partially encapsulates the die pad and the first common electrode bar, such that the bottom surfaces of the die pad and the first common electrode bar are exposed. A length of the first common electrode bar is substantially equal to a predetermined distance between two pads among a plurality of power or ground pads on a side of the die facing the first common electrode bar. An electronic device with the electronic package is also disclosed.Type: GrantFiled: April 23, 2010Date of Patent: October 9, 2012Assignee: Mediatek Inc.Inventors: Nan-Cheng Chen, Nan-Jang Chen, Ching-Chih Li
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Patent number: 8258615Abstract: The present invention provides a semiconductor device capable of eliminating voltage (IR) drop of a semiconductor die inside the semiconductor device and a fabricating method of the semiconductor device. The semiconductor device comprises the semiconductor die, and the semiconductor die comprises a first surface area, a plurality of first pads potentially equivalent to each other, a passivation layer, a plurality of first openings, and a first conducting medium layer. The passivation layer is disposed on the plurality of first pads. The plurality of first openings is formed on the passivation layer, and utilized for exposing the plurality of first pads. The first conducting medium layer is formed on the first surface area, and utilized for fulfilling the plurality of first openings to connect the plurality of first pads.Type: GrantFiled: February 20, 2009Date of Patent: September 4, 2012Assignee: Mediatek Inc.Inventors: Sheng-Ming Chang, Che-Yuan Jao, Ching-Chih Li
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Publication number: 20110248394Abstract: A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads disposed along peripheral edges of the die pad; a ground bar between the leads and the die pad; and a plurality of bridges connecting the ground bar with the die pad, wherein a gap between two adjacent bridges has a length that is equal to or less than 3 mm.Type: ApplicationFiled: April 12, 2011Publication date: October 13, 2011Inventors: Nan-Jang Chen, Chun-Wei Chang, Sheng-Ming Chang, Che-Yuan Jao, Ching-Chih Li, Nan-Cheng Chen
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Patent number: 7880297Abstract: A semiconductor chip includes a die mounted on a packaging substrate. The die includes a semiconductor substrate; inter-metal dielectric layers on the semiconductor substrate; levels of metal interconnection, wherein at least two potential equivalent metal traces are formed in a level of the metal interconnection; a passivation layer disposed over the two metal traces, wherein two openings are formed in the passivation layer to expose portions of the two metal traces; a conductive member externally mounted on the passivation layer between the two openings; and a redistribution layer formed over the conductive member.Type: GrantFiled: May 8, 2008Date of Patent: February 1, 2011Assignee: Mediatek Inc.Inventors: Che-Yuan Jao, Sheng-Ming Chang, Ching-Chih Li
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Patent number: 7816610Abstract: The layout circuit comprises a first 3×2 grid array and a second 3×2 grid array. The first 3×2 grid array comprises first, second and third signal contact points and the first and second fixed potential contact points are coupled to a first fixed potential. The first and second fixed potential contact points are arranged diagonally into the first 2×2 array and the first and second signal contact points are also arranged diagonally into the first 2×2 array. The second 3×2 grid array comprises fourth, fifth and sixth signal contact points and the third and fourth fixed potential contact points are coupled to the first fixed potential. The third and fourth fixed potential contact points are arranged diagonally into the second 2×2 array and the fourth and fifth signal contact points are also arranged diagonally into the second 2×2 array.Type: GrantFiled: September 11, 2007Date of Patent: October 19, 2010Assignee: Mediatek Inc.Inventor: Ching-Chih Li
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Publication number: 20100207260Abstract: An electronic package is provided. The electronic package comprises a die pad having a die attached thereon. A plurality of leads surrounds the die pad and spaced therefrom to define a ring gap therebetween. At least one first common electrode bar is in the ring gap and substantially coplanar to the die pad, in which at least one of the plurality of leads extends to the first common electrode bar. A molding compound partially encapsulates the die pad and the first common electrode bar, such that the bottom surfaces of the die pad and the first common electrode bar are exposed. A length of the first common electrode bar is substantially equal to a predetermined distance between two pads among a plurality of power or ground pads on a side of the die facing the first common electrode bar. An electronic device with the electronic package is also disclosed.Type: ApplicationFiled: April 23, 2010Publication date: August 19, 2010Applicant: MEDIATEK INC.Inventors: Nan-Cheng Chen, Nan-Jang Chen, Ching-Chih Li
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Publication number: 20090224393Abstract: The present invention provides a semiconductor device capable of eliminating voltage (IR) drop of a semiconductor die inside the semiconductor device and a fabricating method of the semiconductor device. The semiconductor device comprises the semiconductor die, and the semiconductor die comprises a first surface area, a plurality of first pads potentially equivalent to each other, a passivation layer, a plurality of first openings, and a first conducting medium layer. The passivation layer is disposed on the plurality of first pads. The plurality of first openings is formed on the passivation layer, and utilized for exposing the plurality of first pads. The first conducting medium layer is formed on the first surface area, and utilized for fulfilling the plurality of first openings to connect the plurality of first pads.Type: ApplicationFiled: February 20, 2009Publication date: September 10, 2009Inventors: Sheng-Ming Chang, Che-Yuan Jao, Ching-Chih Li