Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

Abstract: A semiconductor device and method of manufacture are provided which help to support contacts while material is removed to form air gaps. In embodiments a contact is formed with an enlarged base to help support overlying portions of the contact. In other embodiments a scaffold material may also be placed prior to the formation of the air gaps in order to provide additional support.

Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure is disposed over a substrate and includes a pair of source/drain regions and a gate electrode between the pair of source/drain regions. A lower inter-layer dielectric (ILD) layer is disposed over the pair of source/drain regions and surrounds the gate electrode. The gate electrode is recessed from top of the lower ILD layer. A gate capping layer is disposed on the gate electrode. The gate capping layer has a top surface aligned or coplanar with that of the lower ILD layer.

Abstract: A semiconductor device and method of manufacture are provided which help to support contacts while material is removed to form air gaps. In embodiments a contact is formed with an enlarged base to help support overlying portions of the contact. In other embodiments a scaffold material may also be placed prior to the formation of the air gaps in order to provide additional support.

Abstract: In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.

Abstract: In an embodiment, a structure includes: a contact etch stop layer (CESL) over a substrate; a fin extending through the CESL; an epitaxial source/drain region in the fin, the epitaxial source/drain region extending through the CESL; a silicide contacting upper facets of the epitaxial source/drain region; a source/drain contact contacting the silicide, lower facets of the epitaxial source/drain region, and a first surface of the CESL; and an inter-layer dielectric (ILD) layer surrounding the source/drain contact, the ILD layer contacting the first surface of the CESL.

Abstract: A semiconductor device including source/drain contacts extending into source/drain regions, below topmost surfaces of the source/drain regions, and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region over the semiconductor substrate; a first gate stack over the semiconductor substrate and surrounding four sides of the first channel region; a first epitaxial source/drain region adjacent the first gate stack and the first channel region; and a first source/drain contact coupled to the first epitaxial source/drain region, a bottommost surface of the first source/drain contact extending below a topmost surface of the first channel region.

Abstract: In an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ILD) layer over the source/drain region; a silicide between the first ILD layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ILD layer, the second portion of the first source/drain contact extending through the first ILD layer and contacting the silicide.

Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

Abstract: An embodiment method includes: forming a gate stack over a channel region; growing a source/drain region adjacent the channel region; depositing a first ILD layer over the source/drain region and the gate stack; forming a source/drain contact through the first ILD layer to physically contact the source/drain region; forming a gate contact through the first ILD layer to physically contact the gate stack; performing an etching process to partially expose a first sidewall and a second sidewall, the first sidewall being at a first interface of the source/drain contact and the first ILD layer, the second sidewall being at a second interface of the gate contact and the first ILD layer; forming a first conductive feature physically contacting the first sidewall and a first top surface of the source/drain contact; and forming a second conductive feature physically contacting the second sidewall and a second top surface of the gate contact.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.

Abstract: A method for making a semiconductor device includes forming a first patterned structure over an interlayer dielectric. The interlayer dielectric overlays a first source/drain structure and a second source/drain structure. The first patterned structure extends along a first lateral direction and a vertical projection of the first patterned structure is located between the first and second source/drain structures along a second lateral direction perpendicular to the first lateral direction. The method includes reducing a width of the first patterned structure that extends along the second lateral direction. The method includes forming, based on the first patterned structure having the reduced width, contact holes that expose the first source/drain structure and the second source/drain structure, respectively.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes separating an interlayer dielectric (ILD) into a plurality of portions. The plurality of portions of ILD, separated from each other along a first lateral direction and a second lateral direction, overlay a plurality of groups of epitaxial regions, respectively. The method includes performing an etching process to expose the plurality of groups of epitaxial regions, wherein the etching process comprises a plurality of stages, each of the stages comprising a respective etchant. The method includes forming a plurality of conductive contacts electrically coupled to the plurality of epitaxial regions, respectively.

Abstract: A semiconductor device includes a first source/drain structure coupled to an end of a first conduction channel that extends along a first direction. The semiconductor device includes a second source/drain structure coupled to an end of a second conduction channel that extends along the first direction. The semiconductor device includes a first interconnect structure extending through an interlayer dielectric and electrically coupled to the first source/drain structure. The semiconductor device includes a second interconnect structure extending through the interlayer dielectric and electrically coupled to the second source/drain structure. The semiconductor device includes a first isolation structure disposed between the first and second source/drain structures and extending into the interlayer dielectric.

Abstract: Devices are described herein that include an epitaxial layer, a cap layer above the epitaxial layer, a gate layer adjacent to the epitaxial layer on which an etching process is performed, a trench above the cap layer, and a source/drain portion includes the epitaxial layer.

Abstract: An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug.

Abstract: A semiconductor device includes a substrate, first and second fins protruding from the substrate, and first and second source/drain (S/D) features over the first and second fins respectively. The semiconductor device further includes an isolation feature over the substrate and disposed between the first and second S/D features, and a dielectric layer disposed on sidewalls of the first and second S/D features and on sidewalls of the isolation feature. A top portion of the isolation feature extends above the dielectric layer.

Abstract: An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug.

Abstract: A method includes providing a structure having first and second fins over a substrate and oriented lengthwise generally along a first direction and source/drain (S/D) features over the first and second fins; forming an interlayer dielectric (ILD) layer covering the S/D features; performing a first etching process at least to an area between the S/D features, thereby forming a trench in the ILD layer; depositing a dielectric material in the trench; performing a second etching process to selectively recess the dielectric material; and performing a third etching process to selectively recess the ILD layer, thereby forming a contact hole that exposes the S/D features.

Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.