Patents by Inventor Ching-Feng Fu
Ching-Feng Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200083110Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.Type: ApplicationFiled: November 13, 2019Publication date: March 12, 2020Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
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Publication number: 20200075421Abstract: A method includes providing a structure having first and second fins over a substrate and oriented lengthwise generally along a first direction and source/drain (S/D) features over the first and second fins; forming an interlayer dielectric (ILD) layer covering the S/D features; performing a first etching process at least to an area between the S/D features, thereby forming a trench in the ILD layer; depositing a dielectric material in the trench; performing a second etching process to selectively recess the dielectric material; and performing a third etching process to selectively recess the ILD layer, thereby forming a contact hole that exposes the S/D features.Type: ApplicationFiled: August 9, 2019Publication date: March 5, 2020Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chang-Yun Chang, Ching-Feng Fu, Peng Wang
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Publication number: 20200058765Abstract: Devices are described herein that include an epitaxial layer, a cap layer above the epitaxial layer, a gate layer adjacent to the epitaxial layer on which an etching process is performed, a trench above the cap layer, and a source/drain portion includes the epitaxial layer.Type: ApplicationFiled: October 28, 2019Publication date: February 20, 2020Inventors: Ching-Feng Fu, Yu-Chan Yen, Chih-Hsin Ko, Chun-Hung Lee, Huan-Just Lin, Hui-Cheng Chang
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Patent number: 10504792Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.Type: GrantFiled: December 18, 2018Date of Patent: December 10, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
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Patent number: 10461170Abstract: A method includes providing a semiconductor structure that includes an epitaxial layer and a cap layer above the epitaxial layer, filling a trench above the cap layer with a sacrificial layer, and removing the sacrificial layer. As such, the cap layer is protected by the sacrificial layer during an etching process and the epitaxial layer is protected by the cap layer during another etching process.Type: GrantFiled: May 4, 2016Date of Patent: October 29, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Ching-Feng Fu, Yu-Chan Yen, Chih-Hsin Ko, Chun-Hung Lee, Huan-Just Lin, Hui-Cheng Chang
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Patent number: 10276725Abstract: A method of forming a channel of a gate structure is provided. A first epitaxial channel layer is formed within a first trench of the gate structure. A dry etching process is performed on the first epitaxial channel layer to form a second trench. A second epitaxial channel layer is formed within the second trench.Type: GrantFiled: February 24, 2017Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Ching-Feng Fu, De-Fang Chen, Chun-Hung Lee, Huan-Just Lin, Hui-Cheng Chang
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Publication number: 20190122936Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.Type: ApplicationFiled: December 18, 2018Publication date: April 25, 2019Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
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Patent number: 10163723Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.Type: GrantFiled: April 24, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
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Patent number: 10050149Abstract: A method of forming a semiconductor device includes forming a source/drain region and spacers on a substrate. The method further includes forming an etch stop layer on the spacers and the source/drain region and forming a gate structure between the spacers. The method further includes etching back the gate structure, etching back the spacers and the etch back layer, and forming a gate capping structure on the etched back gate structure, spacers, and etch stop layer.Type: GrantFiled: May 18, 2017Date of Patent: August 14, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Lien Huang, Tsai-Chun Li, Ching-Feng Fu, Ming-Huan Tsai, D. T. Lee, Cheng-Hua Yang, Yi-Chen Lo
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Patent number: 9911661Abstract: A method includes depositing a sacrificial layer on a first dielectric layer over a substrate; applying a first patterning process, a second patterning process, a third patterning process to the sacrificial layer to form a first group of openings, a second group of openings and a third group of openings, respectively, in the sacrificial layer, wherein three first openings from three different patterning processes form a first side, a second side and a first angle between the first side and the second side, and three second openings from the three different patterning processes form a third side, a fourth side and a second angle between the third side and the fourth side, wherein the first angle is approximately equal to the second angle and forming nanowires based on the first group of openings, the second group of openings and the third group of openings.Type: GrantFiled: August 18, 2017Date of Patent: March 6, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
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Patent number: 9911805Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.Type: GrantFiled: November 11, 2016Date of Patent: March 6, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Harry-Hak-Lay Chuang, Bao-Ru Young, Wei Cheng Wu, Kong-Pin Chang, Chia Ming Liang, Meng-Fang Hsu, Ching-Feng Fu, Shih-Ting Hung
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Publication number: 20170365524Abstract: A method includes depositing a sacrificial layer on a first dielectric layer over a substrate; applying a first patterning process, a second patterning process, a third patterning process to the sacrificial layer to form a first group of openings, a second group of openings and a third group of openings, respectively, in the sacrificial layer, wherein three first openings from three different patterning processes form a first side, a second side and a first angle between the first side and the second side, and three second openings from the three different patterning processes form a third side, a fourth side and a second angle between the third side and the fourth side, wherein the first angle is approximately equal to the second angle and forming nanowires based on the first group of openings, the second group of openings and the third group of openings.Type: ApplicationFiled: August 18, 2017Publication date: December 21, 2017Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
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Patent number: 9831322Abstract: A Fin-FET fabrication approach and structure are provided using channel epitaxial regrowth flow (CRF). The method includes forming a Fin-FET structure including a Si line on a substrate, shallow trench isolation (STI) oxide on both sides of the Si line on the substrate, and a poly wall on top of and across the STI oxide and the Si line, wherein the Si line is higher than the STI oxide from the substrate. The method further includes thinning the STI oxide and the Si line while maintaining about the same height ratio of the Si line and the STI oxide, and forming a spacer wall adjacent to both sides of the poly wall and further adjacent to Si and STI oxide side walls under the poly wall uncovered due thinning the STI oxide and the Si line.Type: GrantFiled: June 16, 2016Date of Patent: November 28, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Feng Fu, Shih-Ting Hung, Hsin-Chih Chen, Chih-Hsin Ko, Clement Hsingjen Wann
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Patent number: 9812536Abstract: The present disclosure relate to a method to an integrated chip having a source/drain self-aligned contact to a transistor or other semiconductor device. In some embodiments, the integrated chip has a pair of gate structures including a gate electrode arranged over a substrate and an insulating material arranged over the gate electrode. A source/drain region is arranged within the substrate between the pair of gate structures. An etch stop layer is arranged along sidewalls of the pair of gate structures and over the source/drain region, and a dielectric layer is over the insulating material. A source/drain contact is arranged over the insulating material and the etch stop layer and is separated from the sidewalls of the pair of gate structures by the etch stop layer. The source/drain contact is electrically coupled to the source/drain region.Type: GrantFiled: July 21, 2016Date of Patent: November 7, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Feng Fu, Yu-Chan Yen, Chia-Ying Lee
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Patent number: 9741621Abstract: A method comprises depositing a sacrificial layer on a first dielectric layer over a substrate, applying a first patterning process, a second patterning process, a third patterning process and a fourth patterning process to the sacrificial layer to form a first group of openings, a second group of openings, a third group of openings and a fourth group of openings, respectively, in the sacrificial layer, wherein openings from different patterning processes are arranged in an alternating manner and four openings of the opening from the different patterning processes form a diamond shape and forming nanowires based on the first group of openings, the second group of openings, the third group of openings and the fourth group of openings.Type: GrantFiled: February 10, 2017Date of Patent: August 22, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
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Publication number: 20170229349Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.Type: ApplicationFiled: April 24, 2017Publication date: August 10, 2017Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
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Publication number: 20170162720Abstract: A method of forming a channel of a gate structure is provided. A first epitaxial channel layer is formed within a first trench of the gate structure. A dry etching process is performed on the first epitaxial channel layer to form a second trench. A second epitaxial channel layer is formed within the second trench.Type: ApplicationFiled: February 24, 2017Publication date: June 8, 2017Inventors: Ching-Feng Fu, De-Fang Chen, Chun-Hung Lee, Huan-Just Lin, Hui-Cheng Chang
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Publication number: 20170154824Abstract: A method comprises depositing a sacrificial layer on a first dielectric layer over a substrate, applying a first patterning process, a second patterning process, a third patterning process and a fourth patterning process to the sacrificial layer to form a first group of openings, a second group of openings, a third group of openings and a fourth group of openings, respectively, in the sacrificial layer, wherein openings from different patterning processes are arranged in an alternating manner and four openings of the opening from the different patterning processes form a diamond shape and forming nanowires based on the first group of openings, the second group of openings, the third group of openings and the fourth group of openings.Type: ApplicationFiled: February 10, 2017Publication date: June 1, 2017Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
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Patent number: 9633907Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.Type: GrantFiled: May 28, 2014Date of Patent: April 25, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
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Patent number: 9590090Abstract: A method of forming a channel of a gate structure is provided. A first epitaxial channel layer is formed within a first trench of the gate structure. A dry etching process is performed on the first epitaxial channel layer to form a second trench. A second epitaxial channel layer is formed within the second trench.Type: GrantFiled: January 8, 2014Date of Patent: March 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Ching-Feng Fu, De-Fang Chen, Chun-Hung Lee, Huan-Just Lin, Hui-Cheng Chang