Patents by Inventor Ching-Han Huang

Ching-Han Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250115473
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a substrate with a first groove and a semiconductor device. The first groove has a first portion, a second portion, and a third portion, and the second portion is between the first portion and the third portion. The semiconductor device includes a membrane and is disposed on the second portion of the first groove. The semiconductor device has a first surface adjacent to the substrate and opposite to the membrane. The membrane is exposed by the first surface.
    Type: Application
    Filed: December 17, 2024
    Publication date: April 10, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Liang HSIAO, Lu-Ming LAI, Ching-Han HUANG, Chia-Hung SHEN
  • Publication number: 20250096774
    Abstract: The present disclosure provides a semiconductor package structure. The semiconductor package structure includes a substrate, a first electronic component and a support component. The first electronic component is disposed on the substrate. The first electronic component has a backside surface facing a first surface of the substrate. The support component is disposed between the backside surface of the first electronic component and the first surface of the substrate. The backside surface of the first electronic component has a first portion connected to the support component and a second portion exposed from the support component.
    Type: Application
    Filed: December 3, 2024
    Publication date: March 20, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi Sheng TSENG, Lu-Ming LAI, Ching-Han HUANG, Kuo-Hua LAI, Hui-Chung LIU
  • Patent number: 12184266
    Abstract: The present disclosure provides a semiconductor package structure. The semiconductor package structure includes a substrate, a first electronic component and a support component. The first electronic component is disposed on the substrate. The first electronic component has a backside surface facing a first surface of the substrate. The support component is disposed between the backside surface of the first electronic component and the first surface of the substrate. The backside surface of the first electronic component has a first portion connected to the support component and a second portion exposed from the support component.
    Type: Grant
    Filed: February 21, 2023
    Date of Patent: December 31, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi Sheng Tseng, Lu-Ming Lai, Ching-Han Huang, Kuo-Hua Lai, Hui-Chung Liu
  • Patent number: 12168605
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a substrate with a first groove and a semiconductor device. The first groove has a first portion, a second portion, and a third portion, and the second portion is between the first portion and the third portion. The semiconductor device includes a membrane and is disposed on the second portion of the first groove. The semiconductor device has a first surface adjacent to the substrate and opposite to the membrane. The membrane is exposed by the first surface.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: December 17, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Liang Hsiao, Lu-Ming Lai, Ching-Han Huang, Chia-Hung Shen
  • Patent number: 11973048
    Abstract: A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: April 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: An-Nong Wen, Ching-Han Huang, Ching-Ho Chang
  • Publication number: 20230208394
    Abstract: The present disclosure provides a semiconductor package structure. The semiconductor package structure includes a substrate, a first electronic component and a support component. The first electronic component is disposed on the substrate. The first electronic component has a backside surface facing a first surface of the substrate. The support component is disposed between the backside surface of the first electronic component and the first surface of the substrate. The backside surface of the first electronic component has a first portion connected to the support component and a second portion exposed from the support component.
    Type: Application
    Filed: February 21, 2023
    Publication date: June 29, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi Sheng TSENG, Lu-Ming LAI, Ching-Han HUANG, Kuo-Hua LAI, Hui-Chung LIU
  • Patent number: 11588470
    Abstract: The present disclosure provides a semiconductor package structure. The semiconductor package structure includes a substrate, a first electronic component and a support component. The first electronic component is disposed on the substrate. The first electronic component has a backside surface facing a first surface of the substrate. The support component is disposed between the backside surface of the first electronic component and the first surface of the substrate. The backside surface of the first electronic component has a first portion connected to the support component and a second portion exposed from the support component.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: February 21, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi Sheng Tseng, Lu-Ming Lai, Ching-Han Huang, Kuo-Hua Lai, Hui-Chung Liu
  • Patent number: 11565934
    Abstract: A semiconductor package structure includes a die paddle, a plurality of leads, an electronic component and a package body. Each of the plurality of leads is separated from the die paddle and has an inner side surface facing the die paddle. The electronic component is disposed on the die paddle. The package body covers the die paddle, the plurality of leads and the electronic component. The package body is in direct contact with a bottom surface of the die paddle and the inner side surface of the plurality of leads.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: January 31, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Hsuan Tsai, Lu-Ming Lai, Chien-Wei Fang, Ching-Han Huang
  • Patent number: 11527671
    Abstract: An optical package structure includes a substrate, an emitter, a first detector and a light-absorption material. The substrate has a first surface and a second surface opposite to the first surface, the substrate includes a via defining a third surface extending from the first surface to the second surface. The emitter is disposed on the first surface of the substrate. The first detector is disposed on the first surface and aligned with the via of the substrate. The light-absorption material is disposed on the third surface of the substrate.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: December 13, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi Sheng Tseng, Hui-Chung Liu, Ching-Han Huang
  • Patent number: 11296651
    Abstract: A semiconductor package structure includes an organic substrate having a first surface, a first recess depressed from the first surface, a first chip over the first surface and covering the first recess, thereby defining a first cavity enclosed by a back surface of the first chip and the first recess, and a second chip over the first chip. The first cavity is an air cavity or a vacuum cavity.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: April 5, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi Sheng Tseng, Lu-Ming Lai, Ching-Han Huang, Hui-Chung Liu, Kuo-Hua Lai, Cheng-Ling Huang
  • Publication number: 20220068868
    Abstract: A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.
    Type: Application
    Filed: November 8, 2021
    Publication date: March 3, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: An-Nong WEN, Ching-Han HUANG, Ching-Ho CHANG
  • Patent number: 11171108
    Abstract: A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: November 9, 2021
    Inventors: An-Nong Wen, Ching-Han Huang, Ching-Ho Chang
  • Patent number: 11133278
    Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, a cap layer, a conductive terminal, and a dam structure. The semiconductor die has a first surface. The cap layer is over the semiconductor die and has a second surface facing the first surface of the semiconductor die. The conductive terminal penetrates the cap layer and electrically connects to the semiconductor die. The dam structure is between the semiconductor die and the cap layer and surrounds a portion of the conductive terminal between the first surface and the second surface, thereby forming a gap between the cap layer and the semiconductor die.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: September 28, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Che Huang, Ching-Han Huang, An-Nong Wen, Po-Ming Huang
  • Publication number: 20210276860
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a substrate with a first groove and a semiconductor device. The first groove has a first portion, a second portion, and a third portion, and the second portion is between the first portion and the third portion. The semiconductor device includes a membrane and is disposed on the second portion of the first groove. The semiconductor device has a first surface adjacent to the substrate and opposite to the membrane. The membrane is exposed by the first surface.
    Type: Application
    Filed: May 25, 2021
    Publication date: September 9, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Liang HSIAO, Lu-Ming LAI, Ching-Han HUANG, Chia-Hung SHEN
  • Patent number: 11101189
    Abstract: The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a support structure, an electronic component and an adhesive. The support structure is disposed on the substrate. The electronic component is disposed on the support structure. The adhesive is disposed between the substrate and the electronic component and covers the support structure. A hardness of the support structure is less than a hardness of the electronic component.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: August 24, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming Yen Lee, Chia-Hao Sung, Ching-Han Huang, Yu-Hsuan Tsai
  • Publication number: 20210257988
    Abstract: The present disclosure provides a semiconductor package structure. The semiconductor package structure includes a substrate, a first electronic component and a support component. The first electronic component is disposed on the substrate. The first electronic component has a backside surface facing a first surface of the substrate. The support component is disposed between the backside surface of the first electronic component and the first surface of the substrate. The backside surface of the first electronic component has a first portion connected to the support component and a second portion exposed from the support component.
    Type: Application
    Filed: February 18, 2020
    Publication date: August 19, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi Sheng TSENG, Lu-Ming LAI, Ching-Han HUANG, Kuo-Hua LAI, Hui-Chung LIU
  • Patent number: 11091365
    Abstract: The present disclosure provides a package structure and a manufacturing method. The package structure includes a substrate, a cover, a conductive pattern, and a sensing component. The cover is disposed on the substrate. The cover and the substrate define an accommodation space. The conductive pattern includes a conductive line. The conductive line is disposed on an internal surface of the cover exposed by the accommodation space, and is electrically connected to the substrate. The sensing component is disposed on the internal surface of the cover, and is electrically connected to the conductive line.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: August 17, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ching-Han Huang, Lu-Ming Lai
  • Patent number: 11081413
    Abstract: A semiconductor package structure includes a substrate, a semiconductor die, a lid and a cap. The semiconductor die is disposed on the substrate. The lid is disposed on the substrate. The cap is disposed on the lid. The substrate, the lid and the cap define a cavity in which the semiconductor die is disposed, and a pressure in the cavity is greater than an atmospheric pressure outside the cavity.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: August 3, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsin Lin Wu, Yu-Hsuan Tsai, Chang Chin Tsai, Lu-Ming Lai, Ching-Han Huang
  • Publication number: 20210206628
    Abstract: A semiconductor package structure includes a die paddle, a plurality of leads, an electronic component and a package body. Each of the plurality of leads is separated from the die paddle and has an inner side surface facing the die paddle. The electronic component is disposed on the die paddle. The package body covers the die paddle, the plurality of leads and the electronic component. The package body is in direct contact with a bottom surface of the die paddle and the inner side surface of the plurality of leads.
    Type: Application
    Filed: January 3, 2020
    Publication date: July 8, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Hsuan TSAI, Lu-Ming LAI, Chien-Wei FANG, Ching-Han HUANG
  • Publication number: 20210202780
    Abstract: An optical package structure includes a substrate, an emitter, a first detector and a light-absorption material. The substrate has a first surface and a second surface opposite to the first surface, the substrate includes a via defining a third surface extending from the first surface to the second surface. The emitter is disposed on the first surface of the substrate. The first detector is disposed on the first surface and aligned with the via of the substrate. The light-absorption material is disposed on the third surface of the substrate.
    Type: Application
    Filed: December 31, 2019
    Publication date: July 1, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi Sheng TSENG, Hui-Chung LIU, Ching-Han HUANG