Patents by Inventor Ching-Hua Hsieh

Ching-Hua Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Copper contact plugs with barrier layers
    Patent number: 9136206
    Abstract: A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: September 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Lin Su, Ching-Hua Hsieh, Huang-Ming Chen, Hsueh Wen Tsau
  • Method for integrated circuit patterning
    Patent number: 9129814
    Abstract: A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The method further includes removing at least a portion of the spacer layer to expose the plurality of lines and the substrate. The method further includes shrinking the spacer layer disposed onto the sidewalls of the plurality of lines and removing the plurality of lines thereby resulting in a patterned spacer layer over the substrate.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: September 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ping Tung, Huang-Yi Huang, Neng-Jye Yang, Ching-Hua Hsieh
  • PLASMA APPARATUS, MAGNETIC-FIELD CONTROLLING METHOD, AND SEMICONDUCTOR MANUFACTURING METHOD
    Publication number: 20150235823
    Abstract: Embodiments of a plasma apparatus are provided. The plasma apparatus includes a processing chamber and a wafer chuck disposed in the processing chamber. The plasma apparatus also includes a target element located over the wafer chuck and an electromagnet array located over the target element and having a number of electromagnets. Some of the electromagnets in a magnetic-field zone of the electromagnet array are enabled to generate a magnetic field adjacent to the target element. The magnetic-field zone is moved during a semiconductor manufacturing process.
    Type: Application
    Filed: February 19, 2014
    Publication date: August 20, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chien CHI, Shing-Chyang PAN, Kuan-Chia CHEN, Yao-Jen CHANG, Huang-Yi HUANG, Ching-Hua HSIEH
  • SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20150206840
    Abstract: Embodiments of mechanisms for forming a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure further includes a dielectric layer on the semiconductor substrate. The semiconductor device structure also includes at least one conductive structure embedded in the dielectric layer. A plurality of crystal grains are composed of the conductive structure, and a ratio of an average grain size of the crystal grains to a width of the conductive structure ranges from about 0.75 to about 40.
    Type: Application
    Filed: January 23, 2014
    Publication date: July 23, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chi-Feng LIN, Chih-Chien CHI, Ching-Hua HSIEH
  • Interconnect Structure And Method of Forming
    Publication number: 20150206798
    Abstract: An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a conductive line, and optionally, a cap layer over the conductive line. A treatment is performed to remove impurities prior to forming a layer, e.g., an etch stop layer, ILD, or the like, over the conductive line and/or the cap layer.
    Type: Application
    Filed: January 17, 2014
    Publication date: July 23, 2015
    Inventors: Chih-Chien Chi, Huang-Yi Huang, Szu-Ping Tung, Ching-Hua Hsieh
  • METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE
    Publication number: 20150206791
    Abstract: In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer on a semiconductor substrate. The dielectric layer has at least one first trench in the dielectric layer. The method also includes forming a seed layer on a sidewall and a bottom surface of the first trench. The method further includes forming a first conductive layer on the seed layer. The method includes performing a thermal treatment process to melt and transform the seed layer and the first conductive layer into a second conductive layer. The method also includes forming a third conductive layer on the second conductive layer to fill the first trench.
    Type: Application
    Filed: January 22, 2014
    Publication date: July 23, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Feng LIN, Kuan-Chia CHEN, Ching-Hua HSIEH
  • Systems and Methods for Integrated Resputtering in a Physical Vapor Deposition Chamber
    Publication number: 20150206724
    Abstract: The present disclosure is directed to a material layer deposition system. The material layer deposition system includes a wafer pedestal configured to support at least one wafer within a confinement shield structure and a target carrier structure positioned above the wafer pedestal at an opposite side of the confinement shield structure. The target carrier structure is configured to support a sputtering target. The material layer deposition system further includes a collimator disposed within the confinement shield structure between the wafer pedestal and the target carrier structure, an electrical power source coupled to the collimator to supply electrical power, and a control system configured to control the electrical power source coupled to the collimator.
    Type: Application
    Filed: January 23, 2014
    Publication date: July 23, 2015
    Inventors: Shing-Chyang Pan, Ching-Hua Hsieh, Minghsing Tsai, Syun-Ming Jang
  • Semiconductor Structure With Inlaid Capping Layer And Method Of Manufacturing The Same
    Publication number: 20150200126
    Abstract: A method of fabricating a semiconductor structure includes forming a dielectric layer overlaying a substrate; forming a trench in the dielectric layer; forming a first barrier layer lining the trench; forming a conductive layer overlaying the first barrier layer; forming a second barrier layer overlaying the conductive layer; forming a metallic sacrificial layer to cover the second barrier layer and to fill the trench; and performing a polishing process to remove the materials above a bottom portion of the second barrier layer.
    Type: Application
    Filed: January 15, 2014
    Publication date: July 16, 2015
    Applicant: Taiwan Semiconductor Manufacturing CO., LTD.
    Inventors: Kuan-Chia Chen, Shing-Chyang Pan, Chih-Chien Chi, Ching-Hua Hsieh
  • Metal Capping Process And Processing Platform Thereof
    Publication number: 20150200132
    Abstract: Before depositing a metal capping layer on a metal interconnect in a damascene structure, a remote plasma is used to reduce native oxide formed on the metal interconnect. Accordingly, a remote plasma reducing chamber is integrated in a processing platform for depositing a metal capping layer.
    Type: Application
    Filed: January 15, 2014
    Publication date: July 16, 2015
    Applicant: Taiwan Semiconductor Manufacturing CO., LTD.
    Inventors: Chih-Chien Chi, Szu-Ping Tung, Hung-Yi Huang, Ching-Hua Hsieh
  • Selective Repairing Process For Barrier Layer
    Publication number: 20150201501
    Abstract: A selectively repairing process for a barrier layer is provided. A repair layer is formed by chemical vapor deposition using an organosilicon compound as a precursor gas. The precursor gas adsorbed on a low-k dielectric layer exposed by defects in a barrier layer is transformed to a porous silicon oxide layer has a density more than the density of the low-k dielectric layer.
    Type: Application
    Filed: January 15, 2014
    Publication date: July 16, 2015
    Applicant: Taiwan Semiconductor Manufacturing CO., LTD.
    Inventors: Chih-Chien Chi, Chung-Chi Ko, Mei-Ling Chen, Hung-Yi Huang, Szu-Ping Tung, Ching-Hua Hsieh
  • SELF-ALIGNED REPAIRING PROCESS FOR BARRIER LAYER
    Publication number: 20150194343
    Abstract: A self-aligned repairing process for a barrier layer is provided. A repair layer is formed by chemical vapor deposition using an organometallic compound as a precursor gas. The precursor gas adsorbed on a dielectric layer exposed by defects in a barrier layer is transformed to an insulating metal oxide layer, and the precursor gas adsorbed on the barrier layer is transformed to a metal layer.
    Type: Application
    Filed: January 9, 2014
    Publication date: July 9, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chien CHI, Chung-Chi KO, Mei-Ling CHEN, Hung-Yi HUANG, Szu-Ping TUNG, Ching-Hua HSIEH
  • Surface Pre-Treatment for Hard Mask Fabrication
    Publication number: 20150162280
    Abstract: A robust metallization profile is formed by pre-treat an anti-reflective coating layer by plasma before forming a hard mask layer. Pre-treatment is helpful especially in small feature size process, for example, 50 nm and below. By changing constitution of a surface layer of the anti-reflective coating, interface of the anti-reflective coating layer and the hard mask layer is smoothed which results in less overhang and better gap-filling performance.
    Type: Application
    Filed: December 10, 2013
    Publication date: June 11, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shing-Chyang Pan, Ching-Hua Hsieh, Hong-Hui Hsu, Yao-Jen Chang
  • BI-LAYER HARD MASK FOR ROBUST METALLIZATION PROFILE
    Publication number: 20150162282
    Abstract: A robust metallization profile is formed by forming two or more layers of hard mask with different density. Multi-layer metal hard mask is helpful especially in small feature size process, for example, 50 nm and below. Lower layers have higher density. In such ways, enough process window is offered by lower layers and at the same time, round hard mask profile is offered by upper layers.
    Type: Application
    Filed: December 10, 2013
    Publication date: June 11, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shing-Chyang Pan, Ching-Hua Hsieh, Hong-Hui Hsu
  • Method For Integrated Circuit Patterning
    Publication number: 20150147886
    Abstract: A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The method further includes removing at least a portion of the spacer layer to expose the plurality of lines and the substrate. The method further includes shrinking the spacer layer disposed onto the sidewalls of the plurality of lines and removing the plurality of lines thereby resulting in a patterned spacer layer over the substrate.
    Type: Application
    Filed: November 25, 2013
    Publication date: May 28, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ping Tung, Huang-Yi Huang, Neng-Jye Yang, Ching-Hua Hsieh
  • Structure and Method for Forming Interconnect Structure
    Publication number: 20150123279
    Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate and forming a dielectric layer over the semiconductor substrate. An opening is formed in the dielectric layer. A conductive line is formed in the opening, wherein the conductive line has an open void formed therein. A sealing metal layer is formed overlying the conductive line, the dielectric layer, and the open void, wherein the sealing metal layer substantially fills the open void. The sealing metal layer is planarized so that a top surface thereof is substantially level with a top surface of the conductive line. An interconnect feature is formed above the semiconductor substrate, wherein the interconnect feature is electrically coupled with the conductive line and the sealing metal layer-filled open void.
    Type: Application
    Filed: January 9, 2015
    Publication date: May 7, 2015
    Inventors: Chih-Chien Chi, Huang-Yi Huang, Szu-Ping Tung, Ching-Hua Hsieh
  • Interconnect structures and methods of forming same
    Patent number: 8980745
    Abstract: A semiconductor device, an interconnect structure, and methods of forming the same are disclosed. An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first conductive layer in the first dielectric layer, and removing a first portion of the first conductive layer to form at least two conductive lines in the first dielectric layer, the at least two conductive lines being separated by a first spacing. The method further includes forming a capping layer on the at least two conductive lines, and forming an etch stop layer on the capping layer and the first dielectric layer.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ping Tung, Huang-Yi Huang, Wen-Jiun Liu, Ching-Hua Hsieh, Minghsing Tsai
  • Hard Mask Edge Cover Scheme
    Publication number: 20150072528
    Abstract: A method includes forming at least one trench in a dielectric layer using a hard mask. An edge cover layer is formed over the hard mask. The at least one trench is filled with a metal layer.
    Type: Application
    Filed: September 11, 2013
    Publication date: March 12, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ping Tung, Huang-Yi Huang, Chih-Chien Chi, Ching-Hua Hsieh
  • Semiconductor Devices and Methods of Forming Same
    Publication number: 20150069620
    Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming the same. An embodiment is a method for of forming a semiconductor device, the method including forming a first conductive feature over a substrate, forming a dielectric layer over the conductive feature, and forming an opening through the dielectric layer to the first conductive feature. The method further includes selectively forming a first capping layer over the first conductive feature in the opening, and forming a second conductive feature on the first capping layer.
    Type: Application
    Filed: September 9, 2013
    Publication date: March 12, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Chih-Chien Chi, Huang-Yi Huang, Szu-Ping Tung, Ching-Hua Hsieh
  • INTERCONNECT STRUCTURES AND METHODS OF FORMING SAME
    Publication number: 20150061141
    Abstract: A semiconductor device, an interconnect structure, and methods of forming the same are disclosed. An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first conductive layer in the first dielectric layer, and removing a first portion of the first conductive layer to form at least two conductive lines in the first dielectric layer, the at least two conductive lines being separated by a first spacing. The method further includes forming a capping layer on the at least two conductive lines, and forming an etch stop layer on the capping layer and the first dielectric layer.
    Type: Application
    Filed: September 5, 2013
    Publication date: March 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ping Tung, Huang-Yi Huang, Wen-Jiun Liu, Ching-Hua Hsieh, Minghsing Tsai
  • Structure and method for forming interconnect structure
    Patent number: 8940635
    Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate and forming a dielectric layer over the semiconductor substrate. An opening is formed in the dielectric layer. A conductive line is formed in the opening, wherein the conductive line has an open void formed therein. A sealing metal layer is formed overlying the conductive line, the dielectric layer, and the open void, wherein the sealing metal layer substantially fills the open void. The sealing metal layer is planarized so that a top surface thereof is substantially level with a top surface of the conductive line. An interconnect feature is formed above the semiconductor substrate, wherein the interconnect feature is electrically coupled with the conductive line and the sealing metal layer-filled open void.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Chi, Huang-Yi Huang, Szu-Ping Tung, Ching-Hua Hsieh