Abstract: A barrier layer and a fabrication thereof are disclosed. The barrier layer comprises at least one barrier material selected from the group consisting of Ta, W, Ti, Ru, Zr, Hf, V, Nb, Cr and Mo and at least one component of oxygen, nitrogen or carbon. A ratio of the component to the barrier material is not less than about 0.45. The fabrication method of the barrier layer applies a working pressure for forming the barrier layer from about 0.5 mTorr to about 200 mTorr substantially without forming crystalline material therein.

Abstract: A composite barrier layer provides superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer are generally disposed to form boundaries with dielectric materials and crystalline layers are generally disposed to form boundaries with conductive materials such as interconnect materials.

Abstract: A semiconductor device having a nonconductive cap layer comprising a first metal element. The nonconductive cap layer comprises a first metal nitride, a first metal oxide, or a first metal oxynitride over conductive lines and an insulating material between the conductive lines. An interface region may be formed over the top surface of the conductive lines, the interface region including the metal element of the cap layer. The cap layer prevents the conductive material in the conductive lines from migrating or diffusing into adjacent subsequently formed insulating material layers. The cap layer may also function as an etch stop layer.

Abstract: A new method and structure is provided for the creation of a copper dual damascene interconnect. A dual damascene structure is created in the layer of dielectric, optionally a metal barrier layer is deposited over exposed surfaces of the dual damascene structure. A copper seed layer is deposited, the dual damascene structure is filled with copper. An anneal is applied to the created copper interconnect after which excess copper is removed from the dielectric. Of critical importance to the invention, a thin layer of oxide is then deposited as a cap layer over the copper dual damascene interconnect, an etch stop layer is then deposited over the thin layer of oxide for continued upper-level metallization.

Abstract: A method of reducing the sheet resistivity of an ALD-TaN layer in an interconnect structure. The ALD-TaN layer is treated with a plasma treatment, such as Argon or Tantalum plasma treatment, to increase the Ta/N ratio of the ALD-TaN barrier layer, thereby reducing the sheet resistivity of the ALD-TaN layer.

Abstract: A novel process for re-distributing a barrier layer deposited on a single damascene, dual damascene or other contact opening structure. The process includes providing a substrate having a contact opening structure and a metal barrier layer deposited in the contact opening structure, re-sputtering the barrier layer by bombarding the barrier layer with argon ions and metal ions, and re-sputtering the barrier layer by bombarding the barrier layer with argon ions.

Abstract: A new method and structure is provided for the creation of a copper dual damascene interconnect. A dual damascene structure is created in the layer of dielectric, optionally a metal barrier layer is deposited over exposed surfaces of the dual damascene structure. A copper seed layer is deposited, the dual damascene structure is filled with copper. An anneal is applied to the created copper interconnect after which excess copper is removed from the dielectric. Of critical importance to the invention, a thin layer of oxide is then deposited as a cap layer over the copper dual damascene interconnect, an etch stop layer is then deposited over the thin layer of oxide for continued upper-level metallization.

Abstract: A method for forming a barrier layer upon a copper containing conductor layer employs a hydrogen containing plasma treatment of the copper containing conductor layer followed by an argon plasma treatment of the copper containing conductor layer. The barrier layer may be formed employing a chemical vapor deposition method, such as an atomic layer deposition method. When the deposition method employs a metal and carbon containing source material, the two-step plasma pretreatment provides the barrier layer with enhanced electrical properties.

Abstract: A novel method for depositing a barrier layer on a single damascene, dual damascene or other contact opening structure. The method eliminates the need for pre-cleaning argon ion bombardment of the structure, thereby reducing or eliminating damage to the surface of the underlying conductive layer and sputtering of copper particles to the via or other contact opening sidewall. The process includes fabrication of a single damascene, dual damascene or other contact opening structure on a substrate; optionally pre-cleaning the structure typically using nitrogen or hydrogen plasma; depositing a thin metal barrier layer on the sidewalls and bottom of the structure; and redistributing or re-sputtering the barrier layer on the bottom and sidewalls of the structure.

Abstract: A reactive pre-clean chamber that contains a wafer heating apparatus, such as a high-temperature electrostatic chuck (HTESC), for directly heating a wafer supported on the apparatus during a pre-cleaning process. The wafer heating apparatus is capable of heating the wafer to the optimum temperatures required for a hydrogen plasma reactive pre-clean (RPC) process. Furthermore, degassing and pre-cleaning can be carried out in the same pre-clean chamber. The invention further includes a method of pre-cleaning a wafer using a pre-clean chamber that contains a wafer heating apparatus.

Abstract: A bond pad for a flip chip package. The bond pad is suitable for an integrated circuit chip. A plurality of slots are designed in the bond pad. Each of the slots extends along a direction which is perpendicular to a radial direction from the center of the bond pad. The bond pad is deposed at the corner of the integrated circuit chip.

Abstract: A bond pad for a flip chip package. The bond pad is suitable for an integrated circuit chip. A plurality of slots are designed in the bond pad. Each of the slots extends along a direction which is perpendicular to a radial direction from the center of the bond pad. The bond pad is deposed at the corner of the integrated circuit chip.

Abstract: A method for forming a copper damascene feature including providing a semiconductor process wafer including at least one via opening formed to extend through a thickness of at least one dielectric insulating layer and an overlying trench line opening encompassing the at least one via opening to form a dual damascene opening; etching through an etch stop layer at the at least one via opening bottom portion to expose an underlying copper area; carrying out a sub-atmospheric DEGAS process with simultaneous heating of the process wafer in a hydrogen containing ambient; carrying out an in-situ sputter-clean process; and, forming a barrier layer in-situ to line the dual damascene opening.

Abstract: An atomic layer deposition method is used to deposit a TiN or TiSiN film having a thickness of about 50 nm or less on a substrate. A titanium precursor which is tetrakis(dimethylamido)titanium (TDMAT), tetrakis(diethylamido)titanium (TDEAT), or Ti{OCH(CH3)2}4 avoids halide contamination from a titanium halide precursor and is safer to handle than a titanium nitrate. After a monolayer of the titanium precursor is deposited on a substrate, a nitrogen containing reactant is introduced to form a TiN monolayer which is followed by a second purge. For TiSiN, a silicon source gas is fed into the process chamber after the TiN monolayer formation. The process is repeated several times to produce a composite layer comprised of a plurality of monolayers that fills a contact hole. The ALD method is cost effective and affords an interconnect with lower impurity levels and better step coverage than conventional PECVD or CVD processes.

Abstract: A new method is provided for the creation of a barrier-free copper interconnect. A dual damascene structure is created in a layer of dielectric, a thin metal barrier layer is deposited. The metal barrier layer is oxidized, two layers are then deposited with the first layer comprising doped copper and the second layer comprising pure copper. The dual damascene structure is filled with copper, a thermal anneal is applied, stabilizing the deposited copper filling the dual damascene structure and forming metal oxide of the doped minority element. Excess copper is then removed from the dielectric.

Abstract: A new method and structure is provided for the creation of a copper dual damascene interconnect. A dual damascene structure is created in the layer of dielectric, optionally a metal barrier layer is deposited over exposed surfaces of the dual damascene structure. A copper seed layer is deposited, the dual damascene structure is filled with copper. An anneal is applied to the created copper interconnect after which excess copper is removed from the dielectric. Of critical importance to the invention, a thin layer of oxide is then deposited as a cap layer over the copper dual damascene interconnect, an etch stop layer is then deposited over the thin layer of oxide for continued upper-level metallization.

Abstract: A new method is provided for the creation of a barrier-free copper interconnect. A dual damascene structure is created in a layer of dielectric, a thin metal barrier layer is deposited. The metal barrier layer is oxidized, two layers are then deposited with the first layer comprising doped copper and the second layer comprising pure copper. The dual damascene structure is filled with copper, a thermal anneal is applied, stabilizing the deposited copper filling the dual damascene structure and forming metal oxide of the doped minority element. Excess copper is then removed from the dielectric.

Abstract: A new method is provided of treating the wafer in or on the surface of which a patterned and developed layer of photoresist has been created for the purpose of creating openings in underlying layers of semiconductor material. The wafer is exposed, after the via or plug etch has been completed, to high temperature of between about 250 and 400 degrees C., using a hot plate or a furnace, in an environment of low or atmospheric pressure. The exposure of the wafer to elevated temperatures can be in an environment with or without inert gasses or with or without the presence of a base or forming gas. The dual damascene structure is then completed using a layer of DUV photo, an trench opening is created in the layer of DUV photoresist that aligns with the via opening.

Abstract: A method for in-situ cleaning an electrodeposition surface following an electroplating process including providing a first electrode assembly and a second electrode assembly; applying a first current density across the first electrode assembly and the second electrode assembly for carrying out the electrodeposition process; carrying out the electrodeposition process to electrodeposit a metal onto an electrodeposition surface of the second electrode assembly; and, applying a second current density having a second polarity reversed with reference to the first polarity across the first electrode assembly and the second electrode assembly the second current density having a relatively lower current density compared to the first current density.

Abstract: A new method is provided for the creation of a barrier-free copper interconnect. A dual damascene structure is created in a layer of dielectric, a thin metal barrier layer is deposited. The metal barrier layer is oxidized, two layers are then deposited with the first layer comprising doped copper and the second layer comprising pure copper. The dual damascene structure is filled with copper, a thermal anneal is applied, stabilizing the deposited copper filling the dual damascene structure and forming metal oxide of the doped minority element. Excess copper is then removed from the dielectric.