Abstract: Apparatuses and techniques are described for reducing charge loss in a select gate transistor in a memory device. In one aspect, a dummy memory cell adjacent to a select gate transistor is weakly programmed during an erase operation by applying a program pulse to the dummy memory cell. The program pulse can be applied after an erase bias is applied to the memory cells and before an erase-verify test is performed, in one approach. The program pulse can be applied during the setup of the voltages for the erase-verify test. The magnitude of the program pulse can be increased in successive erase loops of an erase operation as the magnitude of a substrate voltage is also increased. The magnitude of the program pulse can also be set as an increasing function of a number of program-erase (P-E) cycles.

Abstract: Apparatuses and techniques are described for reducing charge loss in a select gate transistor in a memory device. In one aspect, a dummy memory cell adjacent to a select gate transistor is weakly programmed during an erase operation by applying a program pulse to the dummy memory cell. The program pulse can be applied after an erase bias is applied to the memory cells and before an erase-verify test is performed, in one approach. The program pulse can be applied during the setup of the voltages for the erase-verify test. The magnitude of the program pulse can be increased in successive erase loops of an erase operation as the magnitude of a substrate voltage is also increased. The magnitude of the program pulse can also be set as an increasing function of a number of program-erase (P-E) cycles.

Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a buried trench in the substrate and a method of fabricating the same are also discussed. The buried trench is positioned between first and second devices and may be filled with dielectric material. Alternatively, the buried trench contains air. A method of using Hydrogen annealing to create the buried trench is disclosed.

Abstract: Techniques for reducing a downshift in the threshold voltage of a select gate transistor of a memory device. Due to an electric field in a NAND string, holes can move in a charge-trapping layer from a dummy memory cell to a select gate transistor and combine with electrons in the transistor, reducing the threshold voltage. In one approach, the electric field is reduced at the end of a sensing operation by ramping down the voltage of the dummy memory cells before ramping down the voltage of the select gate transistors. The ramp down of the voltage of the selected memory cells can occur after ramping down the voltage of the dummy memory cells and before ramping down of the voltage of the select gate transistors. A further option involves elevating the voltage of the select gate transistors before it is ramped down.

Abstract: An A method for fabricating an integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate is described herein. The trench is self-aligned between the first and second devices and comprises a first portion filled with a dielectric material and a second portion filled with a conductive material. The self-aligned placement of the trench provides electrical isolation between the first and second devices and allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.

Abstract: A memory device and associated techniques for reducing read disturb of memory cells during a sensing process. Select gate transistors are transitioned to a conductive state one or more time during a sensing process, at the drain and/or source ends of the memory strings in an unselected sub-block. The transitioning can occur periodically, multiple times during the sensing process. When the select gate transistors are in a conductive state, accumulated holes in the channel can be removed. This help provide a faster decrease of the channel potential when the unselected word line voltages are ramped down at the end of the sensing process. The duration of a disturb-inducing channel gradient which is created next to the edge data memory cell is reduced so that read disturb of this cell is also reduced.

Abstract: Apparatuses and techniques are described for performing a pre-read operation in preparation for a read operation in a memory device. The pre-read operation transitions the memory cells from a first read condition to a second read condition so that their threshold voltages will be in a desired, predictable range when the read occurs. The pre-read operation can involve maintaining voltages on a selected word line and unselected word lines at specified levels and for a specified duration which is relatively long compared to a duration of the read operation. The word line voltages, in combination with bit line and source line voltages, provide the channels of a NAND string in a conductive state and gradually transitions the memory cells to the second read condition.

Abstract: A memory device and associated techniques for reducing read disturb of memory cells during a sensing process. Select gate transistors are transitioned to a conductive state one or more time during a sensing process, at the drain and/or source ends of the memory strings in an unselected sub-block. The transitioning can occur periodically, multiple times during the sensing process. When the select gate transistors are in a conductive state, accumulated holes in the channel can be removed. This help provide a faster decrease of the channel potential when the unselected word line voltages are ramped down at the end of the sensing process. The duration of a disturb-inducing channel gradient which is created next to the edge data memory cell is reduced so that read disturb of this cell is also reduced.

Abstract: Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, the crept up voltage is not allowed to happen on the memory cell next to the select gate after a sensing operation. In some aspects, the voltage may creep up on the memory cell control gate after a sensing operation, but it is discharged. Reducing and/or preventing the crept up voltage may reduce the electric field between the dummy memory cell and select gate transistor. This may prevent, or at least reduce, changes in threshold voltage of the select gate transistor. Additional problems may also be solved by a reduction of the crept up voltage on the dummy memory cell control gates.

Abstract: Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, the crept up voltage is not allowed to happen on the memory cell next to the select gate after a sensing operation. In some aspects, the voltage may creep up on the memory cell control gate after a sensing operation, but it is discharged. Reducing and/or preventing the crept up voltage may reduce the electric field between the dummy memory cell and select gate transistor. This may prevent, or at least reduce, changes in threshold voltage of the select gate transistor. Additional problems may also be solved by a reduction of the crept up voltage on the dummy memory cell control gates.

Abstract: A memory device and associated techniques to reduce charge loss of memory cells. In one aspect, a charge loss countermeasure is performed if a word line selected for programming is adjacent to a dummy word line. The countermeasure can involve programming the dummy memory cells through injection disturb. In one approach, the timing is adjusted for the voltages on the selected word line and the dummy word line at the end of a program voltage. The selected word line voltage can be decreased more quickly, or the dummy word line voltage can be decreased more slowly. The decrease of the dummy word line voltage can also be delayed. Another approach involves elevating the bit line voltage during the decrease of the selected word line voltage. The bit line voltage can be a function of the assigned data state of a selected cell.

Abstract: Disclosed herein is a non-volatile storage system with memory cells having a charge storage region that may be configured to store a higher density of charges (e.g., electrons) in the middle than nearer to the control gate or channel. The charge storage region has a middle charge storage material that stores a higher density of charges than two outer charge storage materials that are nearer to the control gate or channel, in one aspect. The charge storage region of one aspect has oxide regions between the middle charge storage material and the two outer charge storage materials. The oxide regions of one embodiment are thin (e.g., less than one nanometer) such that during operation charges may easily pass through the oxide regions. The non-volatile memory cell programs quickly and has high data retention.

Abstract: Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a dummy memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, the crept up voltage is not allowed to happen on the dummy memory cell next to the select gate after a sensing operation. In some aspects, the voltage may creep up on the dummy memory cell control gate after a sensing operation, but it is discharged. Reducing and/or preventing the crept up voltage may reduce the electric field between the dummy memory cell and select gate transistor. This may prevent, or at least reduce, changes in threshold voltage of the select gate transistor. Additional problems may also be solved by a reduction of the crept up voltage on the dummy memory cell control gates.

Abstract: A memory device and associated techniques to reduce charge loss of memory cells. In one aspect, a charge loss countermeasure is performed if a word line selected for programming is adjacent to a dummy word line. The countermeasure can involve programming the dummy memory cells through injection disturb. In one approach, the timing is adjusted for the voltages on the selected word line and the dummy word line at the end of a program voltage. The selected word line voltage can be decreased more quickly, or the dummy word line voltage can be decreased more slowly. The decrease of the dummy word line voltage can also be delayed. Another approach involves elevating the bit line voltage during the decrease of the selected word line voltage. The bit line voltage can be a function of the assigned data state of a selected cell.

Abstract: A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation. A pre-charge operation occurs in which a channel voltage is increased to a positive level. This reduces a channel gradient which can lead to a disturb of the select gate transistors. One approach involves applying a voltage at an intermediate level to the source and/or drain ends of the memory strings, before increasing the voltage from the intermediate level to a peak erase level. Another approach involves driving the word line voltages at a negative level and then at a higher level to down couple and then up couple the channel voltages. The techniques may be adjusted depending on whether the word lines are at a positive floating voltage at a start of the erase operation, and based on a level of the floating voltage.

Abstract: Disclosed herein are methods of forming non-volatile storage. An opening may be etched through a stack of two alternating materials to a semiconductor substrate. A silicon nitride film may be formed on a vertical sidewall of the opening. The semiconductor substrate may be cleaned to remove oxide from the semiconductor substrate. The silicon nitride film protects the materials in the stack while cleaning the semiconductor substrate. The silicon nitride film may be converted to an oxide after cleaning the semiconductor substrate. A semiconductor region may be formed in contact with the cleaned semiconductor substrate. A memory cell film may be formed over the oxide in the opening. Control gates may be formed by replacing one of the materials in the stack with a conductive material. The oxide may serve as a blocking layer between the control gates and charge storage regions in the memory cell film.

Abstract: A memory device and associated techniques for reducing charge loss in a select gate transistor. A dummy memory cell is weakly programmed using a hot electron injection type of disturb to reduce the movement of holes toward the adjacent select gate transistor in a common charge trapping layer. The weak programming can occur in a program loop, e.g., in a transition between a pre-charge phase and a program phase, or in an erase loop, just after the erase of dummy and data memory cells. The weak programming does not involve a time penalty since it is concurrent with other operations. The disturb can be provided by increasing the control gate voltage of the dummy memory cell and/or decreasing the control gate voltage of the select gate transistor.

Abstract: A three-dimensional non-volatile memory comprises a plurality of word line layers arranged alternatingly with a plurality of dielectric layers in a stack over a substrate. Higher word lines are implemented to be thicker than lower word lines in order to reduce variation in resistance among word lines.

Abstract: A method for fabricating an integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate is described herein. The trench is self-aligned between the first and second devices and comprises a first portion filled with a dielectric material and a second portion filled with a conductive material. The self-aligned placement of the buried trench provides electrical isolation between the first and second devices and allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.

Abstract: Disclosed herein is a non-volatile storage system with memory cells having a charge storage region that may be configured to store a higher density of charges (e.g., electrons) in the middle than nearer to the control gate or channel. The charge storage region has a middle charge storage material that stores a higher density of charges than two outer charge storage materials that are nearer to the control gate or channel, in one aspect. The charge storage region of one aspect has oxide regions between the middle charge storage material and the two outer charge storage materials. The oxide regions of one embodiment are thin (e.g., less than one nanometer) such that during operation charges may easily pass through the oxide regions. The non-volatile memory cell programs quickly and has high data retention.