Patents by Inventor Ching-Huang Lu
Ching-Huang Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9437470Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. The self-aligned placement of the buried trench isolation allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.Type: GrantFiled: October 8, 2013Date of Patent: September 6, 2016Assignee: Cypress Semiconductor CorporationInventors: Ching-Huang Lu, Lei Xue, Kenichi Ohtsuka, Simon Siu-Sing Chan, Rinji Sugino
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Patent number: 9437305Abstract: Techniques are provided for reducing the effects of short-term charge loss while programming charge-trapping memory cells. Short-term charge loss can result in a downshift and widening of a threshold voltage distribution. A programming operation includes a rough programming pass in which memory cells are programmed close to a final threshold voltage distribution, for each target data state. Subsequently, a negative voltage is applied to control gates of the memory cells. Subsequently, a final programming pass is performed in which the memory cells are programmed to the final threshold voltage distribution. Since the negative voltage accelerates charge loss, there is reduced charge loss after the final programming pass. The rough programming pass can use incremental step pulse programming for the lowest target data state to obtain information regarding programming speed. An initial program voltage in the final programming pass can be set based on the programming speed.Type: GrantFiled: October 28, 2015Date of Patent: September 6, 2016Assignee: SanDisk Technologies LLCInventors: Ching-Huang Lu, Yingda Dong, Liang Pang, Tien-Chien Kuo
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Patent number: 9406387Abstract: Techniques are provided to accelerate the redistribution of the holes in connection with an erase operation, so that there will be a reduced amount of redistribution of the holes after programming. As a result, short-term charge loss after programming is reduced. In one aspect, a positive control gate voltage is applied to a set of memory cells after erase and before programming. The positive control gate voltage has a relatively low amplitude and a long duration, compared to a programming voltage. The positive control gate voltage can be adjusted based on the erase depth of the memory cells and factors such as a count of program-erase cycles, a count of erase-verify iterations, sensing of a position of the lower tail, and a cross-sectional width of a vertical pillar of a memory hole.Type: GrantFiled: September 11, 2015Date of Patent: August 2, 2016Assignee: SanDisk Technologies LLCInventors: Jiahui Yuan, Ching-Huang Lu, Yingda Dong
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Publication number: 20160211271Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.Type: ApplicationFiled: January 26, 2016Publication date: July 21, 2016Inventors: Ching-Huang LU, Simon Siu-Sing CHAN, Hidehiko Shiraiwa, Lei Xue
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Publication number: 20160211321Abstract: A system for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) is disclosed herein. An integrated circuit (IC) comprises a substrate, a first device, a second device, and an isolator. The isolator is positioned between first and second device. The isolator comprises one or more cavities. The isolator may be filled with dielectric material.Type: ApplicationFiled: February 1, 2016Publication date: July 21, 2016Inventors: Rinji Sugino, Lei Xue, Ching-Huang LU, Simon Siu-Sing CHAN
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Patent number: 9378832Abstract: Techniques for reversing damage caused by program-erase cycles in charge-trapping memory to improve long term data retention. A recovery process improves the data retention of a block of memory cells by programming the memory cells to a relatively high threshold voltage and enforcing a time period of several minutes or hours in which the memory cells are inactive and remain at the relatively high Vth levels. Damage such as traps in the memory cells is essentially healed or annealed out during this inactive period. All of the memory cells can be healed at the same time and by relatively equal amounts. At the conclusion of the recovery process, the block is returned to a pool of available blocks. In one approach, an amount of recovery is measured and the period of inactivity is continued for an amount of time which is based on the amount of recovery.Type: GrantFiled: December 10, 2014Date of Patent: June 28, 2016Assignee: SanDisk Technologies Inc.Inventors: Ching-Huang Lu, Zhengyi Zhang, Wei Zhao, Yingda Dong, Jian Chen
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Publication number: 20160172044Abstract: Techniques for reversing damage caused by program-erase cycles in charge-trapping memory to improve long term data retention. A recovery process improves the data retention of a block of memory cells by programming the memory cells to a relatively high threshold voltage and enforcing a time period of several minutes or hours in which the memory cells are inactive and remain at the relatively high Vth levels. Damage such as traps in the memory cells is essentially healed or annealed out during this inactive period. All of the memory cells can be healed at the same time and by relatively equal amounts. At the conclusion of the recovery process, the block is returned to a pool of available blocks. In one approach, an amount of recovery is measured and the period of inactivity is continued for an amount of time which is based on the amount of recovery.Type: ApplicationFiled: December 10, 2014Publication date: June 16, 2016Applicant: SANDISK TECHNOLOGIES INC.Inventors: Ching-Huang Lu, Zhengyi Zhang, Wei Zhao, Yingda Dong, Jian Chen
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Patent number: 9324439Abstract: Techniques are provided to improve long term data retention in a charge-trapping memory device. In addition to a primary charge-trapping layer in which most charges are stored, the memory device may include a tunneling layer comprising an engineered tunneling barrier such as oxide-nitride-oxide. The nitride in the tunneling layer may also store some charges after programming. After the programming, a data retention operation is performed which de-traps some electrons from the tunneling layer, in addition to injecting holes into the tunneling layer which form neutral electron-hole dipoles in place of electrons. These mechanisms tend to lower threshold voltage. Additionally, the data retention operation redistributes the electrons and the holes inside the charge-trapping layer, resulting in an increase in threshold voltage which roughly cancels out the decrease when the data retention operation is optimized.Type: GrantFiled: October 20, 2014Date of Patent: April 26, 2016Assignee: SanDisk Technologies Inc.Inventors: Hong-Yan Chen, Yingda Dong, Ching-Huang Lu
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Publication number: 20160111164Abstract: Techniques are provided to improve long term data retention in a charge-trapping memory device. In addition to a primary charge-trapping layer in which most charges are stored, the memory device may include a tunneling layer comprising an engineered tunneling barrier such as oxide-nitride-oxide. The nitride in the tunneling layer may also store some charges after programming. After the programming, a data retention operation is performed which de-traps some electrons from the tunneling layer, in addition to injecting holes into the tunneling layer which form neutral electron-hole dipoles in place of electrons. These mechanisms tend to lower threshold voltage. Additionally, the data retention operation redistributes the electrons and the holes inside the charge-trapping layer, resulting in an increase in threshold voltage which roughly cancels out the decrease when the data retention operation is optimized.Type: ApplicationFiled: October 20, 2014Publication date: April 21, 2016Applicant: SANDISK TECHNOLOGIES INC.Inventors: Hong-Yan Chen, Yingda Dong, Ching-Huang Lu
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Patent number: 9312010Abstract: Techniques are provided for programming the memory cells of a drain-side edge word line of a set of word lines before programming memory cells of any other word line of the set. Pass voltages applied to the other word lines act as stress pulses which redistribute holes in the charge-trapping material of the memory cells of the other word lines to reduce short-term charge loss and downshifting of the threshold voltage. Additionally, one or more initial program voltages used for the drain-side edge word line are relatively low and also act as stress pulses. The memory cells of the drain-side edge word line are programmed to a narrower Vth window than the memory cells of the other word lines. This compensates for a higher level of program disturb of erased state memory cells of the drain-side edge word line due to reduced channel boosting.Type: GrantFiled: October 7, 2014Date of Patent: April 12, 2016Assignee: SanDisk Technologies Inc.Inventors: Jiahui Yuan, Yingda Dong, Ching-Huang Lu, Wei Zhao
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Publication number: 20160099058Abstract: Techniques are provided for programming the memory cells of a drain-side edge word line of a set of word lines before programming memory cells of any other word line of the set. Pass voltages applied to the other word lines act as stress pulses which redistribute holes in the charge-trapping material of the memory cells of the other word lines to reduce short-term charge loss and downshifting of the threshold voltage. Additionally, one or more initial program voltages used for the drain-side edge word line are relatively low and also act as stress pulses. The memory cells of the drain-side edge word line are programmed to a narrower Vth window than the memory cells of the other word lines. This compensates for a higher level of program disturb of erased state memory cells of the drain-side edge word line due to reduced channel boosting.Type: ApplicationFiled: October 7, 2014Publication date: April 7, 2016Inventors: Jiahui Yuan, Yingda Dong, Ching-Huang Lu, Wei Zhao
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Publication number: 20160064087Abstract: Techniques are provided to accelerate the redistribution of the holes in connection with an erase operation, so that there will be a reduced amount of redistribution of the holes after programming. As a result, short-term charge loss after programming is reduced. In one aspect, a positive control gate voltage is applied to a set of memory cells after erase and before programming. The positive control gate voltage has a relatively low amplitude and a long duration, compared to a programming voltage. The positive control gate voltage can be adjusted based on the erase depth of the memory cells and factors such as a count of program-erase cycles, a count of erase-verify iterations, sensing of a position of the lower tail, and a cross-sectional width of a vertical pillar of a memory hole.Type: ApplicationFiled: August 29, 2014Publication date: March 3, 2016Inventors: Jiahui Yuan, Ching-Huang Lu, Yingda Dong
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Publication number: 20160064084Abstract: Techniques are provided for reducing the effects of short-term charge loss while programming charge-trapping memory cells. Short-term charge loss can result in a downshift and widening of a threshold voltage distribution. A programming operation includes a rough programming pass in which memory cells are programmed close to a final threshold voltage distribution, for each target data state. Subsequently, a negative voltage is applied to control gates of the memory cells. Subsequently, a final programming pass is performed in which the memory cells are programmed to the final threshold voltage distribution. Since the negative voltage accelerates charge loss, there is reduced charge loss after the final programming pass. The rough programming pass can use incremental step pulse programming for the lowest target data state to obtain information regarding programming speed. An initial program voltage in the final programming pass can be set based on the programming speed.Type: ApplicationFiled: October 28, 2015Publication date: March 3, 2016Applicant: SANDISK TECHNOLOGIES INC.Inventors: Ching-Huang Lu, Yingda Dong, Liang Pang, Tien-Chien Kuo
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Publication number: 20160064090Abstract: Techniques are provided to accelerate the redistribution of the holes in connection with an erase operation, so that there will be a reduced amount of redistribution of the holes after programming. As a result, short-term charge loss after programming is reduced. In one aspect, a positive control gate voltage is applied to a set of memory cells after erase and before programming. The positive control gate voltage has a relatively low amplitude and a long duration, compared to a programming voltage. The positive control gate voltage can be adjusted based on the erase depth of the memory cells and factors such as a count of program-erase cycles, a count of erase-verify iterations, sensing of a position of the lower tail, and a cross-sectional width of a vertical pillar of a memory hole.Type: ApplicationFiled: September 11, 2015Publication date: March 3, 2016Applicant: SanDisk Technologies Inc.Inventors: Jiahui Yuan, Ching-Huang Lu, Yingda Dong
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Patent number: 9257191Abstract: Techniques are provided to accelerate the redistribution of the holes in connection with an erase operation, so that there will be a reduced amount of redistribution of the holes after programming. As a result, short-term charge loss after programming is reduced. In one aspect, a positive control gate voltage is applied to a set of memory cells after erase and before programming. The positive control gate voltage has a relatively low amplitude and a long duration, compared to a programming voltage. The positive control gate voltage can be adjusted based on the erase depth of the memory cells and factors such as a count of program-erase cycles, a count of erase-verify iterations, sensing of a position of the lower tail, and a cross-sectional width of a vertical pillar of a memory hole.Type: GrantFiled: August 29, 2014Date of Patent: February 9, 2016Assignee: SanDisk Technologies Inc.Inventors: Jiahui Yuan, Ching-Huang Lu, Yingda Dong
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Patent number: 9252026Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a buried trench in the substrate and a method of fabricating the same are also discussed. The buried trench is positioned between first and second devices and may be filled with dielectric material. Alternatively, the buried trench contains air. A method of using Hydrogen annealing to create the buried trench is disclosed.Type: GrantFiled: March 12, 2014Date of Patent: February 2, 2016Assignee: Cypress Semiconductor CorporationInventors: Rinji Sugino, Lei Xue, Ching-Huang Lu, Simon Chan
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Patent number: 9252154Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.Type: GrantFiled: September 30, 2014Date of Patent: February 2, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Ching-Huang Lu, Simon Siu-Sing Chan, Hidehiko Shiraiwa, Lei Xue
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Patent number: 9230663Abstract: Techniques are provided for reducing the effects of short-term charge loss while programming charge-trapping memory cells. Short-term charge loss can result in a downshift and widening of a threshold voltage distribution. A programming operation includes a rough programming pass in which memory cells are programmed close to a final threshold voltage distribution, for each target data state. Subsequently, a negative voltage is applied to control gates of the memory cells. Subsequently, a final programming pass is performed in which the memory cells are programmed to the final threshold voltage distribution. Since the negative voltage accelerates charge loss, there is reduced charge loss after the final programming pass. The rough programming pass can use incremental step pulse programming for the lowest target data state to obtain information regarding programming speed. An initial program voltage in the final programming pass can be set based on the programming speed.Type: GrantFiled: August 29, 2014Date of Patent: January 5, 2016Assignee: SanDisk Technologies Inc.Inventors: Ching-Huang Lu, Yingda Dong, Liang Pang, Tien-Chien Kuo
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Publication number: 20150262838Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a buried trench in the substrate and a method of fabricating the same are also discussed. The buried trench is positioned between first and second devices and may be filled with dielectric material. Alternatively, the buried trench contains air. A method of using Hydrogen annealing to create the buried trench is disclosed.Type: ApplicationFiled: March 12, 2014Publication date: September 17, 2015Applicant: Spansion LLCInventors: Rinji Sugino, Lei Xue, Ching-Huang Lu, Simon Chan
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Publication number: 20150097245Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. The self-aligned placement of the buried trench isolation allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.Type: ApplicationFiled: October 8, 2013Publication date: April 9, 2015Applicant: Spansion LLCInventors: Ching-Huang LU, Lei Xue, Kenichi Ohtsuka, Simon Siu-Sing Chan, Rinji Sugino