Patents by Inventor Ching-Huang Lu

Ching-Huang Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150097224
    Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is positioned between first and second devices and comprises a first filled portion and a second filled portion. The first filled portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 9, 2015
    Applicant: Spansion LLC
    Inventors: Lei XUE, Ching-Huang LU, Simon Siu-Sing CHAN
  • Publication number: 20150017795
    Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.
    Type: Application
    Filed: September 30, 2014
    Publication date: January 15, 2015
    Inventors: Ching-Huang Lu, Simon Siu-Sing Chan, Hidehiko Shiraiwa, Lei Xue
  • Patent number: 8914969
    Abstract: A method fabricates a magnetic transducer. A sacrificial leading shield is provided on an etch stop layer. A nonmagnetic layer is provided on the sacrificial leading shield. A pole trench is formed in the nonmagnetic layer and on the sacrificial leading shield. A pole is formed. The pole has a bottom and a top wider than the bottom in a pole tip region. Part of the pole in the pole tip region is in the pole trench and at the ABS location. The sacrificial leading shield and part of the nonmagnetic layer adjacent to the pole are removed. An air bridge thus resides in place of the sacrificial leading shield between the portion of the pole and the etch stop layer. As least one shield layer is provided. The at least one shield layer substantially fills the air bridge and form a monolithic shield including a leading and side shields.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: December 23, 2014
    Assignee: Western Digital (Fremont), LLC
    Inventors: Xiaotian Zhou, Hongzhou Jiang, Donghong Li, Lien-Chang Wang, Ching-Huang Lu, Wencheng Su, Lieping Zhong, Tao Pan
  • Patent number: 8866213
    Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: October 21, 2014
    Assignee: Spansion LLC
    Inventors: Ching-Huang Lu, Simon Siu-Sing Chan, Hidehiko Shiraiwa, Lei Xue
  • Publication number: 20140209993
    Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A farther benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.
    Type: Application
    Filed: January 30, 2013
    Publication date: July 31, 2014
    Applicant: Spansion LLC
    Inventors: Ching-Huang LU, Simon Siu-Sing CHAN, Hidehiko SHIRAIWA, Lei XUE
  • Patent number: 8533937
    Abstract: A method or forming a wrapped-around shielded perpendicular magnetic recording writer pole is disclosed. A structure comprising a leading shield layer and an intermediate layer disposed over the leading shield layer is provided, the intermediate layer comprising a pole material and a dielectric material. A trench is formed in the dielectric material. A non-magnetic layer in the trench is removed via an ion beam etching process. A seed layer is deposited in the trench and over the pole material. A magnetic material comprising a side shield layer is deposited on at least a portion of the seed layer.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: September 17, 2013
    Assignee: Western Digital (Fremont), LLC
    Inventors: Jinwen Wang, Weimin Si, Jianxin Fang, Ying Hong, Hongzhou Jiang, Ching-Huang Lu, Yan Chen, Donghong Li, Lien-Chang Wang, Lieping Zhong, Tao Pan
  • Patent number: 8518832
    Abstract: A process is provided for etching a mask layer and removal of residue from a structure having an area sheltered from directional etching. The structure has a shape that forms a silhouette area obstructed from being etched by anisotropic bombardment originating from a first direction, and a mask formed over the mask layer over the structure; A first etch process removes at least a part of the mask layer and retains at least a part of mask layer in the sheltered area. A second etch process removes at least a part of the mask layer in the sheltered area by hydrogen based microwave plasma etching.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: August 27, 2013
    Assignee: Western Digital (Fremont), LLC
    Inventors: Xiaoyu Yang, Xianzhong Zeng, Yan Chen, Yunhe Huang, Jinqiu Zhang, Yang Xiang, Ching-Huang Lu