Patents by Inventor Ching Hwa Tey
Ching Hwa Tey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105502Abstract: A semiconductor structure is provided. The semiconductor structure includes a wafer structure. The wafer structure has a normal region and a trimmed region adjacent to the normal region. A top surface of the trimmed region is lower than a top surface of the normal region. The semiconductor structure includes a dielectric layer and a conductive layer disposed on the wafer structure in the normal region and the trimmed region. The semiconductor structure includes a protective layer disposed on a portion of the dielectric layer in the trimmed region and a portion of the conductive layer in the trimmed region. The semiconductor structure includes another dielectric layer disposed on a portion of the dielectric layer in the normal region and a portion of the conductive layer in the normal region and on the protective layer.Type: ApplicationFiled: December 13, 2023Publication date: March 28, 2024Inventors: Tien-Tsai HUNG, Yi LIU, Guo-Hai ZHANG, Ching-Hwa TEY
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Publication number: 20230387174Abstract: An image sensor structure includes a semiconductor substrate; an interconnection layer on the semiconductor substrate; nano-pillar structures, each including a first doped layer, a second doped layer and a third doped layer stacked in sequence; conductive structures, respectively electrically connected to the first doped layer and the interconnection layer, the second doped layer and the interconnection layer, and the third doped layer and the interconnection layer; a first insulating layer on the interconnection layer and wrapping the nano-pillar structures and the conductive structures, wherein the first doping layer is exposed on the first insulating layer; a transparent barrier layer on the first insulating layer; and a photoelectric thin film structure on the first insulating layer and electrically connected to the interconnection layer. The photoelectric thin film structure includes photoconductive film portions.Type: ApplicationFiled: July 11, 2022Publication date: November 30, 2023Inventors: Zhaoyao Zhan, Jing Feng, XIAOHONG JIANG, CHING HWA TEY
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Publication number: 20230386893Abstract: A semiconductor structure is provided. The semiconductor structure includes a wafer structure. The wafer structure has a normal region and a trimmed region adjacent to the normal region. A top surface of the trimmed region is lower than a top surface of the normal region. The semiconductor structure includes a dielectric layer and a conductive layer disposed on the wafer structure in the normal region and the trimmed region. The semiconductor structure includes a protective layer disposed on a portion of the dielectric layer in the trimmed region and a portion of the conductive layer in the trimmed region. The semiconductor structure includes another dielectric layer disposed on a portion of the dielectric layer in the normal region and a portion of the conductive layer in the normal region and on the protective layer.Type: ApplicationFiled: June 17, 2022Publication date: November 30, 2023Inventors: Tien-Tsai HUNG, Yi LIU, Guo-Hai ZHANG, Ching-Hwa TEY
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Publication number: 20230225139Abstract: The present invention provides an image sensor, the image sensor includes a substrate, a first circuit layer on the substrate, at least one nanowire photodiode located on the first circuit layer and electrically connected with the first circuit layer, wherein the nanowire photodiode comprises a lower material layer and an upper material layer, and a P-N junction or a Schottky junction is arranged between the lower material layer and the upper material layer, wherein the lower material layer comprises a perovskite material, and a precursor layer located under the lower material layer, wherein the precursor layer comprises different metal elements as the lower material layerType: ApplicationFiled: March 17, 2023Publication date: July 13, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Zhaoyao Zhan, QIANWEI DING, XIAOHONG JIANG, CHING HWA TEY
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Patent number: 11641000Abstract: The invention provides an image sensor, the image sensor includes a substrate, a first circuit layer located on the substrate, and at least one nanowire photodiode located on the first circuit layer and electrically connected to the first circuit layer, the nanowire photodiode comprises a lower material layer and an upper material layer with a P-N junction between the lower material layer and the upper material layer, the lower material layer includes perovskite material.Type: GrantFiled: December 29, 2020Date of Patent: May 2, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhaoyao Zhan, Qianwei Ding, Xiaohong Jiang, Ching Hwa Tey
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Publication number: 20230071411Abstract: A method for forming a photosensitive device includes the steps of providing an integrated circuit structure having a first pad and a second pad exposed from a surface of the integrated circuit structure, forming a first material layer on the surface of the integrated circuit structure, patterning the first material layer to expose the second pad, forming a second material layer on the first material layer and covering the second pad, and patterning the second material.Type: ApplicationFiled: November 10, 2022Publication date: March 9, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Zhaoyao Zhan, QIANWEI DING, XIAOHONG JIANG, CHING HWA TEY
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Publication number: 20230076390Abstract: A photosensitive device is disclosed, including an integrated circuit structure, a first pad and a second pad exposed from a surface of the integrated circuit structure, a first material layer disposed on the surface of the integrated circuit structure and covering the first pad, and a second material layer disposed on the first material layer and covering the second pad. The first material layer and the second material layer form a heterojunction photodiode.Type: ApplicationFiled: November 10, 2022Publication date: March 9, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Zhaoyao Zhan, QIANWEI DING, XIAOHONG JIANG, CHING HWA TEY
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Patent number: 11527605Abstract: A method for fabricating a MOMCAP includes steps as follows: An Nth metal layer is formed on a substrate according to an Nth expected capacitance value of the Nth metal layer. An Nth capacitance error value between an Nth actual capacitance value of the Nth metal layer and the Nth expected capacitance value is calculated. An N+1th expected capacitance value of an N+1th metal layer is adjusted to form an N+1th actual capacitance value according to the Nth capacitance error value, and the N+1th metal layer with an N+1th actual capacitance value is formed on the Nth metal layer according to the adjusted N+1th expected capacitance value, to make the sum of the Nth actual capacitance value and the N+1th actual capacitance value equal to the sum of the Nth expected capacitance value and the N+1th expected capacitance value. N is an integer greater than 1.Type: GrantFiled: July 1, 2021Date of Patent: December 13, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shu-Ji Chen, Jing Feng, Xiao-Hong Jiang, Ching-Hwa Tey
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Patent number: 11527561Abstract: A photosensitive device is disclosed, including an integrated circuit structure, a first pad and a second pad exposed from a surface of the integrated circuit structure, a first material layer disposed on the surface of the integrated circuit structure and covering the first pad, and a second material layer disposed on the first material layer and covering the second pad. The first material layer and the second material layer form a photodiode.Type: GrantFiled: July 16, 2020Date of Patent: December 13, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhaoyao Zhan, Qianwei Ding, Xiaohong Jiang, Ching Hwa Tey
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Publication number: 20220367609Abstract: A method for fabricating a MOMCAP includes steps as follows: An Nth metal layer is formed on a substrate according to an Nth expected capacitance value of the Nth metal layer. An Nth capacitance error value between an Nth actual capacitance value of the Nth metal layer and the Nth expected capacitance value is calculated. An N+1th expected capacitance value of an N+1th metal layer is adjusted to form an N+1th actual capacitance value according to the Nth capacitance error value, and the N+1th metal layer with an N+1th actual capacitance value is formed on the Nth metal layer according to the adjusted N+1th expected capacitance value, to make the sum of the Nth actual capacitance value and the N+1th actual capacitance value equal to the sum of the Nth expected capacitance value and the N+1th expected capacitance value. N is an integer greater than 1.Type: ApplicationFiled: July 1, 2021Publication date: November 17, 2022Inventors: Shu-Ji CHEN, Jing FENG, Xiao-Hong JIANG, Ching-Hwa TEY
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Publication number: 20220336519Abstract: An image sensor structure including a substrate, a nanowire structure, a first conductive line, a second conductive line, and a third conductive line is provided. The nanowire structure includes a first doped layer, a second doped layer, a third doped layer, and a fourth doped layer sequentially stacked on the substrate. The first doped layer and the third doped layer have a first conductive type. The second doped layer and the fourth doped layer have a second conductive type. The first conductive line is connected to a sidewall of the second doped layer. The second conductive line is connected to a sidewall of the third doped layer. The third conductive line is connected to the fourth doped layer.Type: ApplicationFiled: May 17, 2021Publication date: October 20, 2022Applicant: United Microelectronics Corp.Inventors: Zhaoyao Zhan, Jing Feng, Qianwei Ding, Xiaohong Jiang, Ching-Hwa Tey
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Publication number: 20220262671Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.Type: ApplicationFiled: May 4, 2022Publication date: August 18, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yunfei Li, JI FENG, GUOHAI ZHANG, CHING HWA TEY
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Patent number: 11355389Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.Type: GrantFiled: December 24, 2020Date of Patent: June 7, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yunfei Li, Ji Feng, Guohai Zhang, Ching Hwa Tey
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Publication number: 20220165895Abstract: The invention provides an image sensor, the image sensor includes a substrate, a first circuit layer located on the substrate, and at least one nanowire photodiode located on the first circuit layer and electrically connected to the first circuit layer, the nanowire photodiode comprises a lower material layer and an upper material layer with a P-N junction between the lower material layer and the upper material layer, the lower material layer includes perovskite material.Type: ApplicationFiled: December 29, 2020Publication date: May 26, 2022Inventors: Zhaoyao Zhan, QIANWEI DING, XIAOHONG JIANG, CHING HWA TEY
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Publication number: 20220139762Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.Type: ApplicationFiled: December 24, 2020Publication date: May 5, 2022Inventors: Yunfei Li, JI FENG, GUOHAI ZHANG, CHING HWA TEY
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Publication number: 20210384231Abstract: A photosensitive device is disclosed, including an integrated circuit structure, a first pad and a second pad exposed from a surface of the integrated circuit structure, a first material layer disposed on the surface of the integrated circuit structure and covering the first pad, and a second material layer disposed on the first material layer and covering the second pad. The first material layer and the second material layer form a photodiode.Type: ApplicationFiled: July 16, 2020Publication date: December 9, 2021Inventors: Zhaoyao Zhan, QIANWEI DING, XIAOHONG JIANG, CHING HWA TEY
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Patent number: 11127621Abstract: A method of forming a semiconductor device includes following steps. Firstly, a substrate is provided and the substrate has a first semiconductor layer formed thereon. Next, an isolating structure is formed in the first semiconductor layer, and a sacrificial layer is formed on the first semiconductor layer by consuming a top portion of the first semiconductor layer. Then, the sacrificial layer is removed to form a second semiconductor layer, and a portion of the isolating structure is also removed to form a shallow trench isolation (STI), with a top surface of the shallow trench isolation being substantially coplanar with a top surface of the second semiconductor layer.Type: GrantFiled: November 4, 2019Date of Patent: September 21, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ji Feng, Yunfei Li, Guohai Zhang, Ching Hwa Tey, Jingling Wang
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Patent number: 11101361Abstract: A GAA transistor includes a semiconductor substrate. A first shallow trench isolation (STI) is embedded in the semiconductor substrate. A top surface of the first STI is lower than a top surface of the semiconductor substrate. A nanowire crosses the first STI and is disposed on the first STI. A gate structure contacts and wraps around the nanowire. A source electrode contacts a first end of the nanowire. A drain electrode contacts a second end of the nanowire.Type: GrantFiled: May 28, 2020Date of Patent: August 24, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhaoyao Zhan, Qianwei Ding, Xiaohong Jiang, Ching Hwa Tey
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Publication number: 20210134653Abstract: A method of forming a semiconductor device includes following steps. Firstly, a substrate is provided and the substrate has a first semiconductor layer formed thereon. Next, an isolating structure is formed in the first semiconductor layer, and a sacrificial layer is formed on the first semiconductor layer by consuming a top portion of the first semiconductor layer. Then, the sacrificial layer is removed to form a second semiconductor layer, and a portion of the isolating structure is also removed to form a shallow trench isolation (STI), with a top surface of the shallow trench isolation being substantially coplanar with a top surface of the second semiconductor layer.Type: ApplicationFiled: November 4, 2019Publication date: May 6, 2021Inventors: JI FENG, Yunfei Li, GUOHAI ZHANG, CHING HWA TEY, JINGLING WANG
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Patent number: 10909299Abstract: A method for stabilizing bandgap voltage includes the steps of: providing a first layout pattern designated with a first voltage; reducing a critical dimension of the first layout pattern for generating a second layout pattern corresponding to a second voltage; matching the second voltage with a target voltage; and then outputting the second layout pattern to a mask. Preferably, the first layout pattern and the second layout pattern include polysilicon resistor patterns.Type: GrantFiled: May 22, 2020Date of Patent: February 2, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei Pang, Jing Feng, Xiaohong Jiang, Ching Hwa Tey