Patents by Inventor Ching Hwa Tey

Ching Hwa Tey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130181264
    Abstract: A semiconductor structure includes at least a fin-shaped structure, a gate, a source/drain region, an interdielectric layer and an epitaxial structure. At least a fin-shaped structure is located on a bottom substrate. The gate covers the fin-shaped structure. The source/drain region is located in the fin-shaped structure next to the gate. The interdielectric layer covers the gate and the fin-shaped structure, wherein the interdielectric layer has a plurality of contact holes, respectively exposing at least a part of the source/drain region. The epitaxial structure is located in each of the contact holes, directly contacts and is only located on the source/drain region. Additionally, a semiconductor process formed said semiconductor structure is also provided.
    Type: Application
    Filed: January 17, 2012
    Publication date: July 18, 2013
    Inventors: Duan Quan Liao, Yikun Chen, Ching-Hwa Tey, Xiao Zhong Zhu
  • Publication number: 20130130460
    Abstract: A method for fabricating a semiconductor device comprises steps as follows: A first dummy gate having a first high-k gate insulator layer, a first composite sacrificial layer, and a first dummy gate electrode sequentially stacked on a substrate is firstly provided. The first dummy gate electrode is subsequently removed to expose the first composite sacrificial layer. The first composite sacrificial layer is then removed. Thereafter, a first work function layer is formed on the first high-k gate insulator layer, and a first metal gate electrode is formed on the first work function layer.
    Type: Application
    Filed: November 17, 2011
    Publication date: May 23, 2013
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Duan-Quan LIAO, Shih-Chieh Hsu, Yi-Kun Chen, Ching-Hwa Tey
  • Publication number: 20120309199
    Abstract: A manufacturing method for a dual damascene structure first includes providing a substrate having at least a dielectric layer, a first hard mask layer, a first cap layer, a second hard mask layer, and a second cap layer sequentially formed thereon, performing a first double patterning process to form a plurality of first trench openings and second trench openings in the second cap layer and the second hard mask, and the first layer being exposed in bottoms of the first trench openings and the second trench openings, performing a second double patterning process to form a plurality of first via openings and second via openings in the first cap layer and the first hard mask layer, and transferring the first trench openings, the second trench openings, the first via openings, and the second via openings to the dielectric layer to form a plurality of dual damascene openings.
    Type: Application
    Filed: August 26, 2011
    Publication date: December 6, 2012
    Inventors: Duan Quan Liao, Yikun Chen, Xiao Zhong Zhu, Ching-Hwa Tey, Chen-Hua Tsai, Yu-Tsung Lai
  • Publication number: 20100173466
    Abstract: A method for fabricating a semiconductor device includes providing a substrate sequentially having a polysilicon layer and an insulating layer formed thereon; patterning the polysilicon layer and the insulating layer to form at least a gate structure on the substrate; forming lightly doped regions in the substrate respectively at two side of the gate structure; forming a spacer on a sidewall of the gate structure; forming barrier layers respectively on a top surface of the gate structure and surfaces of the substrate at two sides of the spacer, and forming a source/drain in the substrate respectively at two sides of the spacer.
    Type: Application
    Filed: January 8, 2009
    Publication date: July 8, 2010
    Inventor: Ching-Hwa Tey
  • Patent number: 7113181
    Abstract: A method of changing display settings of a device (5) for displaying a video signal includes generating new display settings by varying the value of a first display parameter defining the display settings, between a first limit and a second limit; displaying an image on a screen (6) according to the new display settings; and replacing the display settings by the new display settings upon a given command. The new display settings are generated by varying the value of at least one other display parameter defining the display settings simultaneously with the value of the first display parameter.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: September 26, 2006
    Assignee: Koninklijke Philips Electronics N. V.
    Inventors: Ching Hwa Tey, Ngoc Long Freddy Huynh
  • Publication number: 20030090479
    Abstract: A method of changing display settings of a device (5) for displaying a video signal comprises generating new display settings by varying the value of a first display parameter defining the display settings, between a first limit and a second limit; displaying an image on a screen (6) according to the new display settings; and replacing the display settings by the new display settings upon a given command. The new display settings are generated by varying the value of at least one other display parameter defining the display settings simultaneously with the value of the first display parameter.
    Type: Application
    Filed: October 15, 2002
    Publication date: May 15, 2003
    Inventors: Ching Hwa Tey, Ngoc Long Freddy Huynh