Patents by Inventor Ching Hwa Tey
Ching Hwa Tey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10332839Abstract: An interconnect structure including a substrate, at least one ultra-thick metal (UTM) layer, a first dielectric layer and at least one pad metal layer is provided. The at least one UTM layer is disposed on the substrate. The first dielectric layer is disposed on the at least one UTM layer and exposes the at least one UTM layer. A stress of the first dielectric layer is ?150 Mpa to ?500 Mpa. The at least one pad metal layer is disposed on the first dielectric layer and electrically connected to the at least one UTM layer exposed by the first dielectric layer.Type: GrantFiled: January 6, 2017Date of Patent: June 25, 2019Assignee: United Microelectronics Corp.Inventors: Keen Zhang, Ji Feng, De-Jin Kong, Yun-Fei Li, Guo-Hai Zhang, Ching-Hwa Tey, Jing Feng
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Publication number: 20180197819Abstract: An interconnect structure including a substrate, at least one ultra-thick metal (UTM) layer, a first dielectric layer and at least one pad metal layer is provided. The at least one UTM layer is disposed on the substrate. The first dielectric layer is disposed on the at least one UTM layer and exposes the at least one UTM layer. A stress of the first dielectric layer is ?150 Mpa to ?500 Mpa. The at least one pad metal layer is disposed on the first dielectric layer and electrically connected to the at least one UTM layer exposed by the first dielectric layer.Type: ApplicationFiled: January 6, 2017Publication date: July 12, 2018Applicant: United Microelectronics Corp.Inventors: Keen Zhang, Ji Feng, De-Jin Kong, Yun-Fei Li, Guo-Hai Zhang, Ching-Hwa Tey, Jing Feng
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Patent number: 9941161Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon, a first hard mask atop the gate structure, and an interlayer dielectric (ILD) layer around the gate structure and the first hard mask; removing part of the first hard mask; forming a second hard mask layer on the first hard mask and the ILD layer; and planarizing part of the second hard mask layer to form a second hard mask on the first hard mask.Type: GrantFiled: August 28, 2015Date of Patent: April 10, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Duan Quan Liao, Yikun Chen, Ching Hwa Tey
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Patent number: 9698229Abstract: A semiconductor structure includes at least a fin-shaped structure, a gate, a source/drain region, an interdielectric layer and an epitaxial structure. At least a fin-shaped structure is located on a bottom substrate. The gate covers the fin-shaped structure. The source/drain region is located in the fin-shaped structure next to the gate. The interdielectric layer covers the gate and the fin-shaped structure, wherein the interdielectric layer has a plurality of contact holes, respectively exposing at least a part of the source/drain region. The epitaxial structure is located in each of the contact holes, directly contacts and is only located on the source/drain region. Additionally, a semiconductor process formed said semiconductor structure is also provided.Type: GrantFiled: January 17, 2012Date of Patent: July 4, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Duan Quan Liao, Yikun Chen, Ching-Hwa Tey, Xiao Zhong Zhu
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Patent number: 9685387Abstract: A test key and a method for checking the window of a doped region using the test key are provided in the present invention. The test key includes a P-type first well region on a substrate, a P-type substrate region adjacent to the first well region, a N-type first doped region partially overlapping the first well region, two P-type second doped regions at two opposite sides of the first well region, a N-type second well region surrounding the first doped region, the substrate region and the two second doped regions, and a plurality of test pads above the above-identified region.Type: GrantFiled: June 16, 2016Date of Patent: June 20, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhe Wang, Ching Hwa Tey, Lu Zou
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Publication number: 20170162450Abstract: A semiconductor structure includes at least a fin-shaped structure, a gate, a source/drain region, an interdielectric layer and an epitaxial structure. At least a fin-shaped structure is located on a bottom substrate. The gate covers the fin-shaped structure. The source/drain region is located in the fin-shaped structure next to the gate. The interdielectric layer covers the gate and the fin-shaped structure, wherein the interdielectric layer has a plurality of contact holes, respectively exposing at least a part of the source/drain region. The epitaxial structure is located in each of the contact holes, directly contacts and is only located on the source/drain region. Additionally, a semiconductor process formed said semiconductor structure is also provided.Type: ApplicationFiled: February 16, 2017Publication date: June 8, 2017Inventors: Duan Quan Liao, Yikun Chen, Ching-Hwa Tey, Xiao Zhong Zhu
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Publication number: 20170117150Abstract: A semiconductor device includes a hard mask layer and a plurality of spacers. The hard mask layer is disposed on a target layer and has a first material and a second material. The spacers are disposed on the hard mask layer, wherein a first portion of the spacers is disposed on the first material, and a second portion of the spacers is disposed on the second material.Type: ApplicationFiled: January 8, 2017Publication date: April 27, 2017Inventors: Duan Quan Liao, Yikun Chen, CHING HWA TEY
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Patent number: 9583594Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a hard mask layer and a plurality of spacers. The hard mask layer is disposed on a target layer and has a first material and a second material. The spacers are disposed on the hard mask layer, wherein a first portion of the spacers is disposed on the first material, and a second portion of the spacers is disposed on the second material.Type: GrantFiled: August 19, 2015Date of Patent: February 28, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Duan Quan Liao, Yikun Chen, Ching Hwa Tey
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Publication number: 20170040179Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon, a first hard mask atop the gate structure, and an interlayer dielectric (ILD) layer around the gate structure and the first hard mask; removing part of the first hard mask; forming a second hard mask layer on the first hard mask and the ILD layer; and planarizing part of the second hard mask layer to form a second hard mask on the first hard mask.Type: ApplicationFiled: August 28, 2015Publication date: February 9, 2017Inventors: Duan Quan Liao, Yikun Chen, CHING HWA TEY
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Publication number: 20170025519Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a hard mask layer and a plurality of spacers. The hard mask layer is disposed on a target layer and has a first material and a second material. The spacers are disposed on the hard mask layer, wherein a first portion of the spacers is disposed on the first material, and a second portion of the spacers is disposed on the second material.Type: ApplicationFiled: August 19, 2015Publication date: January 26, 2017Inventors: Duan Quan Liao, Yikun Chen, CHING HWA TEY
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Patent number: 9401280Abstract: A semiconductor process includes the following steps. A first gate is formed on a substrate, wherein the first gate includes a stacked gate on the substrate and a cap on the stacked gate. A spacer material is formed to conformally cover the first gate and the substrate. The spacer material is etched to form a spacer on a side of the first gate and a block on the other side of the first gate corresponding to the side. A material covers the substrate, the block, the first gate and the spacer, wherein the top surface of the material is a flat surface. The block, the spacer and the material are pulled down with the same pulling selectivity so that an assisting gate is formed from the block and a selective gate is formed from the spacer.Type: GrantFiled: May 28, 2014Date of Patent: July 26, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Duan Quan Liao, Wei Cheng, Yikun Chen, Ching Hwa Tey, Xiao Zhong Zhu
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Patent number: 9305887Abstract: A method of forming a seal ring structure includes the following steps. A substrate is provided, and the substrate includes a seal ring region. A metal stack is formed in the seal ring region. A first dielectric layer covering the metal stack is formed. A part of the first dielectric layer is removed to form an opening to expose the metal stack, and at least a side of the opening is not perpendicular to a top surface of the first dielectric layer. A conductive layer is formed to fill the opening. A second dielectric layer is formed to continuously cover the first dielectric layer and the conductive layer, and the second dielectric layer has a v-shaped surface totally overlapping the conductive layer.Type: GrantFiled: June 5, 2013Date of Patent: April 5, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fan-Qing Zeng, Ching Hwa Tey, Xiaoqing Xu
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Patent number: 9276057Abstract: A capacitor structure includes a substrate with a plurality of dielectric layers sequentially formed thereon, a trench formed in the dielectric layers, wherein the trench is composed of at least two interconnected dual damascene recesses, each dual damascene recess formed in one dielectric layer; and a capacitor multilayer disposed on the sidewall of the trench.Type: GrantFiled: January 27, 2014Date of Patent: March 1, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Duan Quan Liao, Yikun Chen, Ching Hwa Tey, Xiao Zhong Zhu
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Publication number: 20150348789Abstract: A semiconductor process includes the following steps. A first gate is formed on a substrate, wherein the first gate includes a stacked gate on the substrate and a cap on the stacked gate. A spacer material is formed to conformally cover the first gate and the substrate. The spacer material is etched to form a spacer on a side of the first gate and a block on the other side of the first gate corresponding to the side. A material covers the substrate, the block, the first gate and the spacer, wherein the top surface of the material is a flat surface. The block, the spacer and the material are pulled down with the same pulling selectivity so that an assisting gate is formed from the block and a selective gate is formed from the spacer.Type: ApplicationFiled: May 28, 2014Publication date: December 3, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Duan Quan Liao, Wei Cheng, Yikun Chen, CHING HWA TEY, Xiao Zhong Zhu
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Publication number: 20150214293Abstract: A capacitor structure includes a substrate with a plurality of dielectric layers sequentially formed thereon, a trench formed in the dielectric layers, wherein the trench is composed of at least two interconnected dual damascene recesses, each dual damascene recess formed in one dielectric layer; and a capacitor multilayer disposed on the sidewall of the trench.Type: ApplicationFiled: January 27, 2014Publication date: July 30, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Duan Quan Liao, Yikun Chen, CHING HWA TEY, Xiao Zhong Zhu
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Publication number: 20150140800Abstract: A method of fabricating a semiconductor device includes the following steps. At least a first gate stack layer and at least a second gate stack layer protruding from a conductive layer on a substrate are provided. Subsequently, two spacers and a protective layer are formed on the conductive layer, and the two spacers and the protective layer jointly surround the protruded first gate stack layer and the protruded second gate stack layer. The two spacers and the protective layer are used as a mask to remove a part of the conductive layer. Afterwards, the two spacers and the protective layer are removed.Type: ApplicationFiled: November 18, 2013Publication date: May 21, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wei Cheng, Ming Sheng Xu, Duan Quan Liao, Yikun Chen, CHING HWA TEY
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Patent number: 9023726Abstract: A method of fabricating a semiconductor device includes the following steps. At least a first gate stack layer and at least a second gate stack layer protruding from a conductive layer on a substrate are provided. Subsequently, two spacers and a protective layer are formed on the conductive layer, and the two spacers and the protective layer jointly surround the protruded first gate stack layer and the protruded second gate stack layer. The two spacers and the protective layer are used as a mask to remove a part of the conductive layer. Afterwards, the two spacers and the protective layer are removed.Type: GrantFiled: November 18, 2013Date of Patent: May 5, 2015Assignee: United Microelectronics Corp.Inventors: Wei Cheng, Ming Sheng Xu, Duan Quan Liao, Yikun Chen, Ching Hwa Tey
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Publication number: 20140361438Abstract: A method of forming a seal ring structure includes the following steps. A substrate is provided, and the substrate includes a seal ring region. A metal stack is formed in the seal ring region. A first dielectric layer covering the metal stack is formed. A part of the first dielectric layer is removed to form an opening to expose the metal stack, and at least a side of the opening is not perpendicular to a top surface of the first dielectric layer. A conductive layer is formed to fill the opening. A second dielectric layer is formed to continuously cover the first dielectric layer and the conductive layer, and the second dielectric layer has a v-shaped surface totally overlapping the conductive layer.Type: ApplicationFiled: June 5, 2013Publication date: December 11, 2014Inventors: Fan-Qing Zeng, Ching Hwa Tey, Xiaoqing Xu
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Patent number: 8828878Abstract: A manufacturing method for a dual damascene structure first includes providing a substrate having at least a dielectric layer, a first hard mask layer, a first cap layer, a second hard mask layer, and a second cap layer sequentially formed thereon, performing a first double patterning process to form a plurality of first trench openings and second trench openings in the second cap layer and the second hard mask, and the first layer being exposed in bottoms of the first trench openings and the second trench openings, performing a second double patterning process to form a plurality of first via openings and second via openings in the first cap layer and the first hard mask layer, and transferring the first trench openings, the second trench openings, the first via openings, and the second via openings to the dielectric layer to form a plurality of dual damascene openings.Type: GrantFiled: August 26, 2011Date of Patent: September 9, 2014Assignee: United Microelectronics Corp.Inventors: Duan Quan Liao, Yikun Chen, Xiao Zhong Zhu, Ching-Hwa Tey, Chen-Hua Tsai, Yu-Tsung Lai
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Patent number: 8658487Abstract: A method for fabricating a semiconductor device comprises steps as follows: A first dummy gate having a first high-k gate insulator layer, a first composite sacrificial layer, and a first dummy gate electrode sequentially stacked on a substrate is firstly provided. The first dummy gate electrode is subsequently removed to expose the first composite sacrificial layer. The first composite sacrificial layer is then removed. Thereafter, a first work function layer is formed on the first high-k gate insulator layer, and a first metal gate electrode is formed on the first work function layer.Type: GrantFiled: November 17, 2011Date of Patent: February 25, 2014Assignee: United Microelectronics Corp.Inventors: Duan-Quan Liao, Shih-Chieh Hsu, Yi-Kun Chen, Ching-Hwa Tey