Patents by Inventor Ching-I Li
Ching-I Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210273123Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed in a semiconductor substrate. The photodetector comprises a first doped region having a first doping type. A deep well region is disposed within the semiconductor substrate, where the deep well region extends from a back-side surface of the semiconductor substrate to a top surface of the first doped region. A second doped region is disposed within the semiconductor substrate and abuts the first doped region. The second doped region and the deep well region comprise a first dopant having a second doping type opposite the first doping type, where the first dopant comprises gallium.Type: ApplicationFiled: September 18, 2020Publication date: September 2, 2021Inventors: Kai-Yun Yang, Chun-Yuan Chen, Ching I Li
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Patent number: 11107689Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a pad oxide layer on the substrate, wherein the pad oxide layer comprises a first thickness; performing an implantation process to inject germanium (Ge) into the substrate on the PMOS region; performing a first cleaning process to reduce the first thickness of the pad oxide layer on the PMOS region to a second thickness; performing an anneal process; and performing a second cleaning process to remove the pad oxide layer.Type: GrantFiled: December 3, 2018Date of Patent: August 31, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shi-You Liu, Tsai-Yu Wen, Ming-Shiou Hsieh, Rong-Sin Lin, Ching-I Li, Neng-Hui Yang
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Publication number: 20200235208Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.Type: ApplicationFiled: April 1, 2020Publication date: July 23, 2020Inventors: Shi-You Liu, Tsai-Yu Wen, Ching-I Li, Ya-Yin Hsiao, Chih-Chiang Wu, Yu-Chun Liu, Ti-Bin Chen, Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu
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Patent number: 10651275Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.Type: GrantFiled: February 11, 2018Date of Patent: May 12, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shi-You Liu, Tsai-Yu Wen, Ching-I Li, Ya-Yin Hsiao, Chih-Chiang Wu, Yu-Chun Liu, Ti-Bin Chen, Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu
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Publication number: 20200144064Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a pad oxide layer on the substrate, wherein the pad oxide layer comprises a first thickness; performing an implantation process to inject germanium (Ge) into the substrate on the PMOS region; performing a first cleaning process to reduce the first thickness of the pad oxide layer on the PMOS region to a second thickness; performing an anneal process; and performing a second cleaning process to remove the pad oxide layer.Type: ApplicationFiled: December 3, 2018Publication date: May 7, 2020Inventors: Shi-You Liu, Tsai-Yu Wen, Ming-Shiou Hsieh, Rong-Sin Lin, Ching-I Li, Neng-Hui Yang
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Patent number: 10468502Abstract: A FinFET device includes a substrate, first and second fins, first and second gates and first and second epitaxial layers. The substrate has a first region and a second region. The first and second fins are on the substrate respectively in the first and second regions. In an embodiment, the number of the first fins is different from the number of the second fins. The first and second gates are on the substrate and respectively across the first and second fins. The first epitaxial layers are disposed in first recesses of the first fins adjacent to the first gate. The second epitaxial layers are disposed in second recesses of the second fins adjacent to the second gate. In an embodiment, the maximum width of the first epitaxial layers is L1, the maximum width of the second epitaxial layers is L2, and (L2?L1)/L1 is equal to or less than about 1%.Type: GrantFiled: January 22, 2019Date of Patent: November 5, 2019Assignee: United Microelectronics Corp.Inventors: Chun-Liang Kuo, Tsang-Hsuan Wang, Yu-Ming Hsu, Tsung-Mu Yang, Ching-I Li
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Publication number: 20190229202Abstract: A FinFET device includes a substrate, first and second fins, first and second gates and first and second epitaxial layers. The substrate has a first region and a second region. The first and second fins are on the substrate respectively in the first and second regions. In an embodiment, the number of the first fins is different from the number of the second fins. The first and second gates are on the substrate and respectively across the first and second fins. The first epitaxial layers are disposed in first recesses of the first fins adjacent to the first gate. The second epitaxial layers are disposed in second recesses of the second fins adjacent to the second gate. In an embodiment, the maximum width of the first epitaxial layers is L1, the maximum width of the second epitaxial layers is L2, and (L2?L1)/L1 is equal to or less than about 1%.Type: ApplicationFiled: January 22, 2019Publication date: July 25, 2019Applicant: United Microelectronics Corp.Inventors: Chun-Liang Kuo, Tsang-Hsuan Wang, Yu-Ming Hsu, Tsung-Mu Yang, Ching-I Li
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Publication number: 20190214465Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.Type: ApplicationFiled: February 11, 2018Publication date: July 11, 2019Inventors: Shi-You Liu, Tsai-Yu Wen, Ching-I Li, Ya-Yin Hsiao, Chih-Chiang Wu, Yu-Chun Liu, Ti-Bin Chen, Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu
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Patent number: 10263096Abstract: A FinFET device includes a substrate, first and second fins, first and second gates and first and second epitaxial layers. The substrate has a first region and a second region. The first and second fins are on the substrate respectively in the first and second regions. In an embodiment, the number of the first fins is different from the number of the second fins. The first and second gates are on the substrate and respectively across the first and second fins. The first epitaxial layers are disposed in first recesses of the first fins adjacent to the first gate. The second epitaxial layers are disposed in second recesses of the second fins adjacent to the second gate. In an embodiment, the maximum width of the first epitaxial layers is L1, the maximum width of the second epitaxial layers is L2, and (L2?L1)/L1 is equal to or less than about 1%.Type: GrantFiled: January 24, 2018Date of Patent: April 16, 2019Assignee: United Microelectronics Corp.Inventors: Chun-Liang Kuo, Tsang-Hsuan Wang, Yu-Ming Hsu, Tsung-Mu Yang, Ching-I Li
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Publication number: 20190067477Abstract: A semiconductor structure includes a substrate, fin-shaped structures disposed on the substrate, an isolation layer disposed between the fin-shaped structures, and a doped region disposed in an upper portion of the isolation layer, where the doped region is doped with helium or neon.Type: ApplicationFiled: August 28, 2017Publication date: February 28, 2019Inventors: Shi-You Liu, Ming-Shiou Hsieh, Rong-Sin Lin, Han-Ting Yen, Tsai-Yu Wen, Ching-I Li
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Publication number: 20180108570Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.Type: ApplicationFiled: November 19, 2017Publication date: April 19, 2018Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Neng-Hui Yang, Tsai-Yu Wen, Ching-I Li
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Patent number: 9947588Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.Type: GrantFiled: November 19, 2017Date of Patent: April 17, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Neng-Hui Yang, Tsai-Yu Wen, Ching-I Li
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Patent number: 9859164Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.Type: GrantFiled: October 17, 2016Date of Patent: January 2, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Neng-Hui Yang, Tsai-Yu Wen, Ching-I Li
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Patent number: 9748072Abstract: In an exemplary process for lower dose rate ion implantation of a work piece, an ion beam may be generated using an ion source and an extraction manipulator. The extraction manipulator may be positioned at a gap distance from an exit aperture of the ion source. A current of the ion beam exiting the extraction manipulator may be maximized when the extraction manipulator is positioned at an optimal gap distance from the exit aperture. The gap distance at which the extraction manipulator is positioned from the exit aperture may differ from the optimal gap distance by at least 10 percent. A first potential may be applied to a first set of electrodes. An x-dimension of the ion beam may increase as the ion beam passes through the first set of electrodes. The work piece may be positioned in the ion beam to implant ions into the work piece.Type: GrantFiled: June 23, 2014Date of Patent: August 29, 2017Assignee: ADVANCED ION BEAM TECHNOLOGY, INC.Inventors: Zhimin Wan, Rekha Padmanabhan, Xiao Bai, Gary N. Cai, Ching-I Li, Ger-Pin Lin, Shao-Yu Hu, David Hoglund, Robert E. Kaim, Kourosh Saadatmand
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Publication number: 20160293734Abstract: In forming a punch-through stopper region in a fin field effect transistor (finFET) device, a substrate may be etched to form a pair of trenches that define a fin structure. A portion of a first dose of ions may be implanted into the substrate through a bottom wall of each trench to form a pair of first dopant regions that at least partially extend under a channel region of the fin structure. The substrate at the bottom wall of each trench may be etched to increase a depth of each trench. Etching the substrate at the bottom wall of each trench may remove a portion of each first dopant region under each trench. A remaining portion of the pair of first dopant regions under the fin structure may at least partially define the punch-through stopper region of the finFET device.Type: ApplicationFiled: April 3, 2015Publication date: October 6, 2016Inventors: Daniel TANG, Zhimin WAN, Ching-I LI, Ger-Pin LIN
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Patent number: 9450078Abstract: In forming a punch-through stopper region in a fin field effect transistor (finFET) device, a substrate may be etched to form a pair of trenches that define a fin structure. A portion of a first dose of ions may be implanted into the substrate through a bottom wall of each trench to form a pair of first dopant regions that at least partially extend under a channel region of the fin structure. The substrate at the bottom wall of each trench may be etched to increase a depth of each trench. Etching the substrate at the bottom wall of each trench may remove a portion of each first dopant region under each trench. A remaining portion of the pair of first dopant regions under the fin structure may at least partially define the punch-through stopper region of the finFET device.Type: GrantFiled: April 3, 2015Date of Patent: September 20, 2016Assignee: ADVANCED ION BEAM TECHNOLOGY, INC.Inventors: Daniel Tang, Zhimin Wan, Ching-I Li, Ger-Pin Lin
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Patent number: 9431247Abstract: A method for an ion implantation is provided. First, a non-parallel ion beam is provided. Thereafter, a relative motion between a workpiece and the non-parallel ion beam, so as to enable each region of the workpiece to be implanted by different portions of the non-parallel ion beam successively. Particularly, when at least one three-dimensional structure is located on the upper surface of the workpiece, both the top surface and the side surface of the three-dimensional structure may be implanted properly by the non-parallel ion beam when the workpiece is moved across the non-parallel ion beam one and only one times. Herein, the non-parallel ion beam can be a divergent ion beam or a convergent ion beam (both may be viewed as the integrated divergent beam), also can be generated directly from an ion source or is modified from a parallel ion beam, a divergent ion beam or a convergent ion beam.Type: GrantFiled: June 26, 2015Date of Patent: August 30, 2016Assignee: ADVANCED ION BEAM TECHNOLOGY, INC.Inventors: Zhimin Wan, Kourosh Saadatmand, Wilhelm P. Platow, Ger-Pin Lin, Ching-I Li, Rekha Padmanabhan, Gary N. Cai
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Publication number: 20160133469Abstract: A method for an ion implantation is provided. First, a non-parallel ion beam is provided. Thereafter, a relative motion between a workpiece and the non-parallel ion beam, so as to enable each region of the workpiece to be implanted by different portions of the non-parallel ion beam successively. Particularly, when at least one three-dimensional structure is located on the upper surface of the workpiece, both the top surface and the side surface of the three-dimensional structure may be implanted properly by the non-parallel ion beam when the workpiece is moved across the non-parallel ion beam one and only one times. Herein, the non-parallel ion beam can be a divergent ion beam or a convergent ion beam (both may be viewed as the integrated divergent beam), also can be generated directly from an ion source or is modified from a parallel ion beam, a divergent ion beam or a convergent ion beam.Type: ApplicationFiled: June 26, 2015Publication date: May 12, 2016Inventors: Zhimin WAN, Kourosh SAADATMAND, Wilhelm P. PLATOW, Ger-Pin LIN, Ching-I LI, Rekha PADMANABHA, Gary N. CAI
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Publication number: 20150371857Abstract: In an exemplary process for lower dose rate ion implantation of a work piece, an ion beam may be generated using an ion source and an extraction manipulator. The extraction manipulator may be positioned at a gap distance from an exit aperture of the ion source. A current of the ion beam exiting the extraction manipulator may be maximized when the extraction manipulator is positioned at an optimal gap distance from the exit aperture. The gap distance at which the extraction manipulator is positioned from the exit aperture may differ from the optimal gap distance by at least 10 percent. A first potential may be applied to a first set of electrodes. An x-dimension of the ion beam may increase as the ion beam passes through the first set of electrodes. The work piece may be positioned in the ion beam to implant ions into the work piece.Type: ApplicationFiled: June 23, 2014Publication date: December 24, 2015Inventors: Zhimin WAN, Rekha PADMANABHAN, Xiao BAI, Gary N. CAI, Ching-I LI, Ger-Pin LIN, Shao-Yu HU, David HOGLUND, Robert E. KAIM, Kourosh SAADATMAND
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Publication number: 20150104914Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. The polysilicon layer is cryo-implanted with at least two of multiple species including a germanium species, a carbon species and a p- or n-type species, at a temperature ranging between ?40° C. and ?120° C. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.Type: ApplicationFiled: November 24, 2014Publication date: April 16, 2015Inventors: Chan-Lon Yang, Ching-Nan Hwang, Chi-Heng Lin, Chun-Yao Yang, Ger-Pin Lin, Ching-I Li