Patents by Inventor Ching-I Li
Ching-I Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8921206Abstract: First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below ?30° C.Type: GrantFiled: November 30, 2011Date of Patent: December 30, 2014Assignee: United Microelectronics Corp.Inventors: Chan-Lon Yang, Ching-I Li, Ger-Pin Lin, I-Ming Lai, Yun-San Huang, Chin-I Liao, Chin-Cheng Chien
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Patent number: 8883620Abstract: A novel process for using enriched and highly enriched dopant gases is provided herein that eliminates the problems currently encountered by end-users from being able to realize the process benefits associated with ion implanting such dopant gases. For a given flow rate within a prescribed range, operating at a reduced total power level of the ion source is designed to reduce the ionization efficiency of the enriched dopant gas compared to that of its corresponding non-enriched or lesser enriched dopant gas. The temperature of the source filament is also reduced, thereby mitigating the adverse effects of fluorine etching and ion source shorting when a fluorine-containing enriched dopant gas is utilized. The reduced levels of total power in combination with a lower ionization efficiency and lower ion source temperature can interact synergistically to improve and extend ion source life, while beneficially maintaining a beam current that does not unacceptably deviate from previously qualified levels.Type: GrantFiled: April 24, 2013Date of Patent: November 11, 2014Assignee: Praxair Technology, Inc.Inventors: Ashwini K. Sinha, Ching I Li
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Publication number: 20140322902Abstract: A novel process for using enriched and highly enriched dopant gases is provided herein that eliminates the problems currently encountered by end-users from being able to realize the process benefits associated with ion implanting such dopant gases. For a given flow rate within a prescribed range, operating at a reduced total power level of the ion source is designed to reduce the ionization efficiency of the enriched dopant gas compared to that of its corresponding non-enriched or lesser enriched dopant gas. The temperature of the source filament is also reduced, thereby mitigating the adverse effects of fluorine etching and ion source shorting when a fluorine-containing enriched dopant gas is utilized. The reduced levels of total power in combination with a lower ionization efficiency and lower ion source temperature can interact synergistically to improve and extend ion source life, while beneficially maintaining a beam current that does not unacceptably deviate from previously qualified levels.Type: ApplicationFiled: April 24, 2013Publication date: October 30, 2014Inventors: Ashwini K. Sinha, Ching I. Li
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Publication number: 20130337622Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.Type: ApplicationFiled: August 20, 2013Publication date: December 19, 2013Applicant: United Microelectronics Corp.Inventors: Chan-Lon Yang, Ching-Nan Hwang, Chi-Heng Lin, Chun-Yao Yang, Ger-Pin Lin, Ching-I Li
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Patent number: 8575043Abstract: A semiconductor device includes a plurality of active areas disposed on a semiconductor substrate. A manufacturing method of the semiconductor device includes performing a first annealing process on the semiconductor substrate by emitting a first laser alone a first scanning direction, and performing a second annealing process on the semiconductor substrate by emitting a second laser alone a second scanning direction. The first scanning direction and the second scanning direction have an included angle.Type: GrantFiled: July 26, 2011Date of Patent: November 5, 2013Assignee: United Microelectronics Corp.Inventors: Chan-Lon Yang, Tzu-Feng Kuo, Hsin-Huei Wu, Ching-I Li, Shu-Yen Chan
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Publication number: 20130264585Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a recess and a stress-providing structure. A channel structure is formed in the substrate. The recess is formed in the substrate and arranged beside the channel structure. The recess has a round inner surface. The stress-providing structure is formed within the recess. Corresponding to the profile of the round inner surface of the recess, the stress-providing structure has a round outer surface.Type: ApplicationFiled: June 3, 2013Publication date: October 10, 2013Inventors: Chin-I LIAO, Ching-Hong JIANG, Ching-I LI, Shu-Yen CHAN, Chin-Cheng CHIEN
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Patent number: 8536072Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.Type: GrantFiled: February 7, 2012Date of Patent: September 17, 2013Assignee: United Microelectronics Corp.Inventors: Chan-Lon Yang, Ching-Nan Hwang, Chi-Heng Lin, Chun-Yao Yang, Ger-Pin Lin, Ching-I Li
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Publication number: 20130203226Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a forntside heating is different from a power for a backside heating.Type: ApplicationFiled: February 7, 2012Publication date: August 8, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chan-Lon Yang, Ching-Nan Hwang, Chi-Heng Lin, Chun-Yao Yang, Ger-Pin Lin, Ching-I Li
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Patent number: 8486790Abstract: A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate.Type: GrantFiled: July 18, 2011Date of Patent: July 16, 2013Assignee: United Microelectronics Corp.Inventors: Po-Cheng Huang, Kuo-Chih Lai, Ching-I Li, Yu-Shu Lin, Ya-Jyuan Hung, Yen-Liang Lu, Yu-Wen Wang, Hsin-Chih Yu
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Patent number: 8481391Abstract: A process for manufacturing a stress-providing structure is applied to the fabrication of a semiconductor device. Firstly, a substrate with a channel structure is provided. A silicon nitride layer is formed over the substrate by chemical vapor deposition in a halogen-containing environment. An etching process is performed to partially remove the silicon nitride layer to expose a portion of a surface of the substrate beside the channel structure. The exposed surface of the substrate is etched to form a recess in the substrate. Then, the substrate is thermally treated at a temperature between 750° C. and 820° C. After the substrate is thermally treated, a stress-providing material is filled in the recess to form a stress-providing structure within the recess. The semiconductor device includes a substrate, a recess and a stress-providing structure. The recess has a round inner surface. The stress-providing structure has a round outer surface.Type: GrantFiled: May 18, 2011Date of Patent: July 9, 2013Assignee: United Microelectronics Corp.Inventors: Chin-I Liao, Ching-Hong Jiang, Ching-I Li, Shu-Yen Chan, Chin-Cheng Chien
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Publication number: 20130137243Abstract: First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below ?30° C.Type: ApplicationFiled: November 30, 2011Publication date: May 30, 2013Inventors: Chan-Lon Yang, Ching-I Li, Ger-Pin Lin, I-Ming Lai, Yun-San Huang, Chin-I Liao, Chin-Cheng Chien
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Publication number: 20130026543Abstract: A semiconductor device includes a plurality of active areas disposed on a semiconductor substrate. A manufacturing method of the semiconductor device includes performing a first annealing process on the semiconductor substrate by emitting a first laser alone a first scanning direction, and performing a second annealing process on the semiconductor substrate by emitting a second laser alone a second scanning direction. The first scanning direction and the second scanning direction have an incident angle.Type: ApplicationFiled: July 26, 2011Publication date: January 31, 2013Inventors: Chan-Lon Yang, Tzu-Feng Kuo, Hsin-Huei Wu, Ching-I Li, Shu-Yen Chan
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Publication number: 20130023103Abstract: A method for fabricating a semiconductor device is implemented by using a stress memorization technique. The method includes the following steps. Firstly, a substrate is provided, wherein a gate structure is formed over the substrate. Then, a pre-amorphization implantation process is performed to define an amorphized region at a preset area of the substrate with the gate structure serving as an implantation mask. During the pre-amorphization implantation process is performed, the substrate is controlled at a temperature lower than room temperature. Then, a stress layer is formed on the gate structure and a surface of the amorphized region. Then, a thermal treatment process is performed to re-crystallize the amorphized region of the substrate. Afterwards, the stress layer is removed.Type: ApplicationFiled: July 19, 2011Publication date: January 24, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chan-Lon YANG, Ching-I LI, Ger-Pin LIN
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Publication number: 20130023098Abstract: A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate.Type: ApplicationFiled: July 18, 2011Publication date: January 24, 2013Inventors: Po-Cheng Huang, Kuo-Chih Lai, Ching-I Li, Yu-Shu Lin, Ya-Jyuan Hung, Yen-Liang Lu, Yu-Wen Wang, Hsin-Chih Yu
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Publication number: 20120292638Abstract: A process for manufacturing a stress-providing structure is applied to the fabrication of a semiconductor device. Firstly, a substrate with a channel structure is provided. A silicon nitride layer is formed over the substrate by chemical vapor deposition in a halogen-containing environment. An etching process is performed to partially remove the silicon nitride layer to expose a portion of a surface of the substrate beside the channel structure. The exposed surface of the substrate is etched to form a recess in the substrate. Then, the substrate is thermally treated at a temperature between 750° C. and 820° C. After the substrate is thermally treated, a stress-providing material is filled in the recess to form a stress-providing structure within the recess. The semiconductor device includes a substrate, a recess and a stress-providing structure. The recess has a round inner surface. The stress-providing structure has a round outer surface.Type: ApplicationFiled: May 18, 2011Publication date: November 22, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chin-I LIAO, Ching-Hong Jiang, Ching-I Li, Shu-Yen Chan, Chin-Cheng Chien
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Patent number: 8273642Abstract: A SiC region and a source/drain region are formed such that the SiC region includes a first portion overlapping the source/drain region and a second portion protruding from the source/drain region to a position beneath the LDD region. The concentration of crystalline SiC in the second portion is higher than the concentration of crystalline SiC in the first portion. The SiC region may be formed through a normal implantation before the second spacer is formed, or the SiC region may be formed through a tilt implantation or deposition epitaxially in a recess having a sigma-shape like sidewall after the second spacer is formed.Type: GrantFiled: October 4, 2010Date of Patent: September 25, 2012Assignee: United Microelectronics Corp.Inventors: Chen-Hua Tsai, Po-Jui Liao, Tzu-Feng Kuo, Ching-I Li, Cheng-Tzung Tsai
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Publication number: 20120080721Abstract: A semiconductor structure includes a recess disposed in a substrate, a non-doped epitaxial layer and a doped epitaxial layer. The non-doped epitaxial layer is disposed on the inner surface of the recess and substantially consists of Si and an epitaxial layer. The non-doped epitaxial layer has a sidewall and a bottom which together cover the inner surface. The bottom thickness is not greater than 120% of the sidewall thickness. The non-doped epitaxial layer and the doped epitaxial layer together fill up the recess.Type: ApplicationFiled: October 4, 2010Publication date: April 5, 2012Inventors: Chin-I Liao, Ching-I Li, Shu-Yen Chan
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Publication number: 20120083090Abstract: A SiC region and a source/drain region are formed such that the SiC region includes a first portion overlapping the source/drain region and a second portion protruding from the source/drain region to a position beneath the LDD region. The concentration of crystalline SiC in the second portion is higher than the concentration of crystalline SiC in the first portion. The SiC region may be formed through a normal implantation before the second spacer is formed, or the SiC region may be formed through a tilt implantation or deposition epitaxially in a recess having a sigma-shape like sidewall after the second spacer is formed.Type: ApplicationFiled: October 4, 2010Publication date: April 5, 2012Inventors: Chen-Hua Tsai, Po-Jui Liao, Tzu-Feng Kuo, Ching-I Li, Cheng-Tzung Tsai
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Patent number: 8076210Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a first ion implantation process to implant a first molecular cluster having carbon, boron, and hydrogen into the semiconductor substrate at two sides of the gate structure for forming a doped region, wherein the molecular weight of the first molecular cluster is greater than 100.Type: GrantFiled: March 8, 2011Date of Patent: December 13, 2011Assignee: United Microelectronics Corp.Inventors: Tsai-Fu Hsiao, Ching-I Li, Po-Yuan Chen, Chun-An Lin, Hsiang-Ying Wang, Chao-Chun Chen, Chin-Cheng Chien
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Patent number: 8053847Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing carbon, boron, and hydrogen into the semiconductor substrate at two sides of the spacer for forming a doped region. The molecular weight of the molecular cluster is preferably greater than 100. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the doped region.Type: GrantFiled: November 28, 2008Date of Patent: November 8, 2011Assignee: United Microelectronics Corp.Inventors: Tsai-Fu Hsiao, Ching-I Li, Po-Yuan Chen, Chun-An Lin, Hsiang-Ying Wang, Chao-Chun Chen, Chin-Cheng Chien