Patents by Inventor Ching Lin

Ching Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250006734
    Abstract: An integrated circuit (IC) device includes a stripe of material perpendicular to, and spanning between, semiconductor structures with multiple widths, and the stripe is between transistors with channel regions of differing widths in the semiconductor structures. The material stripes cover transition portions between different widths of the semiconductor structures. The semiconductor structures may be channel structures of different types, including groups of fins or nanoribbons. Channel regions of differing widths may include more or fewer fins or narrower or wider nanoribbons. The channel regions may have alternating conductivity types, n- and p-type.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Tao Chu, Minwoo Jang, Yanbin Luo, Paul Packan, Guowei Xu, Chiao-Ti Huang, Robin Chao, Feng Zhang, Ting-Hsiang Hung, Chia-Ching Lin, Yang Zhang, Chung-Hsun Lin
  • Publication number: 20250008693
    Abstract: A heat-dissipating element having a casing having a closed fluid space. At least a part of the fluid space is filled with a coolant fluid, and the coolant fluid is transformed between a liquid phase and a gas phase by an environment temperature transferred by the casing.
    Type: Application
    Filed: June 27, 2024
    Publication date: January 2, 2025
    Inventors: Tzu-Chia TAN, YAO-CHUN WANG, WEN-HUNG LIN, WEN-YUAN CHOU, PO-CHING LIN, SHANTI KARTIKA SARI
  • Publication number: 20250003933
    Abstract: Embodiments are disclosed of an active flow control system including one or more inlets and one or more outlets. A first outlet is configured to be fluidly coupled to an inlet of a mini-environment, and a first is configured to be coupled to an outlet of the mini-environment. The active flow control system includes one or more flow control configurations; each flow control configuration corresponds to a flow control mode. The one or more flow configurations include a configuration corresponding to a sampling mode. The sampling mode includes injecting a neutral fluid from the first outlet into the inlet of the mini-environment, and directing a mixed fluid exiting through the outlet of the mini-environment to the first inlet of the active flow control system, the mixed fluid being a combination of the neutral fluid and the fluid that was in the mini-environment before injecting the neutral fluid into the mini-environment.
    Type: Application
    Filed: June 27, 2024
    Publication date: January 2, 2025
    Inventors: Tsung-Kuan A. Chou, Li-Peng Wang, Ching-Lin Hsiao, Wei-Shao Tung
  • Publication number: 20240424133
    Abstract: The present disclosure provides compositions and methods for mRNA therapy with reduced immune reactogenicity.
    Type: Application
    Filed: January 24, 2024
    Publication date: December 26, 2024
    Inventors: Isabel M. CHU, Yang XIANG, Stefano GULLA, Jason J. ZHANG, Paulo Jia Ching LIN, Ying K. TAM
  • Patent number: 12176388
    Abstract: A transistor structure includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source material coupled to a first end of the first and second channel layers, a drain material coupled to a second end of the first and second channel layers, a gate electrode between the source material and the drain material, and between the first channel layer and the second channel layer and a gate dielectric between the gate electrode and each of the first channel layer and the second channel layer.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: December 24, 2024
    Assignee: Intel Corporation
    Inventors: Kevin O'Brien, Chelsey Dorow, Kirby Maxey, Carl Naylor, Shriram Shivaraman, Sudarat Lee, Tanay Gosavi, Chia-Ching Lin, Uygar Avci, Ashish Verma Penumatcha
  • Patent number: 12175155
    Abstract: Disclosed is a wireless transmission system, including a mobile electronic device with first screen information, a computer with second screen information, and a docking station coupled to the computer. When accommodating the mobile electronic device, the docking station transmits an electrical signal to the mobile electronic device, wherein the computer confirms that the mobile electronic device is located on the docking station according to a Bluetooth Low Energy signal sent by the mobile electronic device, the computer transmits Wi-Fi service set identification information to the mobile electronic device through a Bluetooth Low Energy protocol, the computer and the mobile electronic device are connected to the same Wi-Fi access point, and the mobile electronic device sends the first screen information back to the computer. Accordingly, the problem that the computer and the mobile electronic device cannot transmit data or screen information to each other through a transmission line is solved.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: December 24, 2024
    Assignee: LANTO ELECTRONIC LIMITED
    Inventors: Chih-Hsiung Chang, Chia-Ching Lin
  • Publication number: 20240405746
    Abstract: A bulk acoustic wave resonant structure and a preparation method therefor, and an acoustic wave device are provided. The bulk acoustic wave resonant structure includes: a substrate; a reflection structure, a first electrode, a piezoelectric layer and a second electrode, which are successively located on the substrate, wherein the first electrode comprises a first sub-electrode located in a first region and a second sub-electrode located in a second region other than the first region, and the piezoelectric layer respectively comes into direct contact with the first sub-electrode and the second electrode in the first region; and a first gap, which is located between the piezoelectric layer and the second sub-electrode, wherein an orthographic projection of the first gap on the substrate surrounds the first region.
    Type: Application
    Filed: September 23, 2022
    Publication date: December 5, 2024
    Applicant: WUHAN YANXI MICRO COMPONENTS CO., LTD.
    Inventors: Zhi Wei KOH, Re-Ching LIN, Pei-Chun LIAO, Wei-sheng HUANG, Dapeng ZHANG
  • Patent number: 12156659
    Abstract: Provided herein is an IVRO surgical guide for positioning a cutting guide on a mandibular ramus such that the mandibular ramus is clamped between a hooked distal end and a slidable component having a curved claw. The cutting guide is placed at a predetermined distance from the posterior edge of the ramus at the mid-waistline of the mandibular ramus along a curvilinear shaft in contact with the lateral surface of the ramus. The cutting guide can accommodate a saw for performing the osteotomy.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: December 3, 2024
    Assignee: Vanderbilt University
    Inventors: Susie I Ching Lin, Kevin C Galloway
  • Patent number: 12159400
    Abstract: A real time assay monitoring system and method can be used to monitor reagent volume in assays for fluid replenishment control, monitor assays in real-time to obtain quality control information, monitor assays in real-time during development to detect saturation levels that can be used to shorten assay time, and provide assay results before the assay is complete, enabling reflex testing to begin automatically. The monitoring system can include a real time imaging system with a camera and lights to capture images of the assay. The captured images can then be used to monitor and control the quality of the staining process in an assay, provide early assay results, and/or to measure the on-site reagent volume within the assay.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: December 3, 2024
    Assignee: Ventana Medical Systems, Inc.
    Inventors: Yu-Heng Cheng, Setareh Duquette, Lisa A. Jones, Chih-Ching Lin, Javier Andres Perez-Sepulveda
  • Publication number: 20240396523
    Abstract: Embodiments of the present disclosure provide a bulk acoustic wave resonance structure and a preparation method therefor, and an acoustic wave device. The bulk acoustic wave resonance structure comprises: a substrate; a reflection structure, a first electrode, a piezoelectric layer, and a second electrode, which are sequentially located on the substrate, the effective region of a resonance area being a first overlapping area; a first surrounding structure surrounding the first overlapping area, said structure comprising first protruding structures and first intermittent structures that are arranged at intervals; and the first protruding structures, which are located between the piezoelectric layer and the first electrode and/or are located between the piezoelectric layer and the second electrode, the end of each first protruding structure that is close to the first overlapping area being covered by the first electrode and/or the second electrode.
    Type: Application
    Filed: September 23, 2022
    Publication date: November 28, 2024
    Applicant: WUHAN YANXI MICRO COMPONENTS CO., LTD.
    Inventors: Re-Ching LIN, Dapeng ZHANG, Pei-Chun LIAO, Wei-sheng HUANG, Zhi Wei KOH
  • Publication number: 20240387239
    Abstract: A manufacturing method of a semiconductor structure includes the following steps. Fin-shaped structures are formed by patterning a first region of a semiconductor substrate. A first shallow trench is formed in a second region of the semiconductor substrate. A part of the semiconductor substrate is exposed by a bottom of the first shallow trench. A first etching process is performed. At least a part of one of the fin-shaped structures is removed by the first etching process, and the part of the semiconductor substrate exposed by the first shallow trench is partially removed by the first etching process for forming a first deep trench. The manufacturing method of the present invention may be used to achieve the purposes of process simplification and/or manufacturing cost reduction.
    Type: Application
    Filed: June 14, 2023
    Publication date: November 21, 2024
    Inventors: Po-Tsang Chen, Chia-Ching Lin, Wen-Liang Huang
  • Publication number: 20240376158
    Abstract: Provided herein are engineered hMPV F proteins. In some aspects, the engineered F proteins exhibit enhanced conformational stability and/or antigenicity. Methods are also provided for use of the engineered F proteins as diagnostics, in screening platforms, and/or in vaccine compositions.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Applicant: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
    Inventors: Jason McLELLAN, Ching-Lin HSIEH, Scott RUSH, Nianshuang WANG
  • Publication number: 20240381636
    Abstract: A semiconductor device includes a substrate, a first film stack, a second film stack, a first gate spacer, a buffer layer, and a second gate spacer. The first and second film stacks are located on the substrate, and are respectively located in an array area and a periphery area. The first gate spacer includes a first portion on a sidewall of the first film stack and a second portion on a sidewall of the second film stack. The buffer layer includes a first portion on a sidewall of the first portion of the first gate spacer and a second portion on a sidewall of the second portion of the first gate spacer. The second gate spacer includes a first portion on a sidewall of the first portion of the buffer layer and a second portion on a sidewall the second portion of the buffer layer.
    Type: Application
    Filed: May 12, 2023
    Publication date: November 14, 2024
    Inventor: Chih-Ching LIN
  • Publication number: 20240369885
    Abstract: A display device includes a substrate, a semiconductor, an electrode, a first conductive layer and a second conductive layer. The semiconductor is disposed on the substrate. The electrode is disposed on the substrate. The electrode is electrically connected to the semiconductor. The first conductive layer is overlapped with the electrode. The first conductive layer has a first opening. The second conductive layer is overlapped with the electrode. The second conductive layer has a second opening. The second conductive layer is closer to the substrate than the first conductive layer, and an area of the second opening is greater than an area of the first opening.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Applicant: Innolux Corporation
    Inventors: Feng-Ching Lin, Chia-Wei Tseng, Wen-Ming Hung, Shu-Hui Chang
  • Publication number: 20240356203
    Abstract: An artificial-reality device comprising (1) an eyewear frame dimensioned to be worn by a user and (2) a plurality of antennas coupled to the eyewear frame, wherein the plurality of antennas comprise (A) a first antenna configured to support a first wireless technology, (B) a second antenna configured to support a second wireless technology, and (C) a third antenna configured to support a third wireless technology. Various other apparatuses, systems, and methods are also disclosed.
    Type: Application
    Filed: April 18, 2023
    Publication date: October 24, 2024
    Inventors: Nil Apaydin, Vignesh Manohar, Javier Rodriguez De Luis, Chia-Ching Lin, Huan Liao, Liang Han
  • Patent number: 12125893
    Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: October 22, 2024
    Assignee: Intel Corporation
    Inventors: Tanay Gosavi, Chia-Ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • Patent number: 12125895
    Abstract: A transistor includes a channel including a first layer including a first monocrystalline transition metal dichalcogenide (TMD) material, where the first layer is stoichiometric and includes a first transition metal. The channel further includes a second layer above the first layer, the second layer including a second monocrystalline TMD material, where the second monocrystalline TMD material includes a second transition metal and oxygen, and where the second layer is sub-stoichiometric. The transistor further includes a gate electrode above a first portion of the channel layer, a gate dielectric layer between the channel layer and the gate electrode, a source contact on a second portion of the channel layer and a drain contact on a third portion of the channel layer, where the gate electrode is between drain contact and the source contact.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: October 22, 2024
    Assignee: Intel Corporation
    Inventors: Chelsey Dorow, Kevin O'Brien, Carl Naylor, Uygar Avci, Sudarat Lee, Ashish Verma Penumatcha, Chia-Ching Lin, Tanay Gosavi, Shriram Shivaraman, Kirby Maxey
  • Patent number: 12117918
    Abstract: Systems and methods are disclosed for determining an engagement level of a user interacting with an electronic program, comprising receiving or determining a decision node tree, each node in the decision node tree corresponding to a user decision point in the electronic program, determining a number of levels in the decision node tree, determining a user traversed count comprising a number of levels the user has traversed in the decision node tree, and determining the engagement level of the user with the electronic program based upon the user traversed count and the number of levels in the decision node tree.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: October 15, 2024
    Assignee: Yahoo Ad Tech LLC
    Inventors: Osnat Benari, Ruiheng Wang, Sasinda Rukshan Premarathna, Cheng Li, Bhagyasri Canumalla, Hsiao-Ching Lin, Yanbo Li, Davood Shamsi
  • Patent number: 12113117
    Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: October 8, 2024
    Assignee: Intel Corporation
    Inventors: Tanay Gosavi, Chia-ching Lin, Raseong Kim, Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • Patent number: RE50258
    Abstract: A projection device includes a light source module, an optical engine module, a projection lens, a housing, and at least one first heat dissipating element. The housing comprises a first end and a second end opposite to each other. The at least one first heat dissipating element is disposed in the housing, and each of the at least one first heat dissipating element includes a first plate portion, a second plate portion, and a first fin portion. The first plate portion is connected to the light source module. The second plate portion is connected to the first plate portion. The first fin portion is connected to the second plate portion and includes a plurality of first fins arranged at intervals. These first fins are arranged between the first end and the second end.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: December 31, 2024
    Assignee: Coretronic Corporation
    Inventors: Jhih-Hao Chen, Wei-Min Chien, Tsung-Ching Lin, Shi-Wen Lin