Patents by Inventor CHING-NEN PENG
CHING-NEN PENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11852672Abstract: A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.Type: GrantFiled: July 27, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTORMANUFACTURING COMPANY LIMITEDInventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Chuan-Ching Wang, Hao Chen
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Patent number: 11726112Abstract: A circuit probe includes a shielding probe having a base and a conductive probe ring on the base. A shielding cage is attached to the conductive probe ring and has an interior. The shielding cage is configured to be positioned to contain in the interior of the shielding cage at least one integrated circuit formed on a wafer, and to provide electromagnetic shielding of the at least one integrated circuit during testing of the at least one integrated circuit.Type: GrantFiled: September 16, 2019Date of Patent: August 15, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Nen Peng, Hsien-Tang Wang, Mill-Jer Wang, Chi-Chang Lai
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Patent number: 11579190Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.Type: GrantFiled: May 23, 2022Date of Patent: February 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Mill-Jer Wang, Kuo-Chuan Liu, Ching-Nen Peng, Hung-Chih Lin, Hao Chen
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Publication number: 20220357389Abstract: A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.Type: ApplicationFiled: July 27, 2022Publication date: November 10, 2022Inventors: Mill-Jer WANG, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Chuan-Ching Wang, Hao Chen
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Patent number: 11467203Abstract: A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.Type: GrantFiled: July 27, 2020Date of Patent: October 11, 2022Inventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Chuan-Ching Wang, Hao Chen
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Publication number: 20220283221Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.Type: ApplicationFiled: May 23, 2022Publication date: September 8, 2022Inventors: Mill-Jer WANG, Kuo-Chuan LIU, Ching-Nen PENG, Hung-Chih LIN, Hao CHEN
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Patent number: 11387683Abstract: An integrated circuit (IC) includes a first circuit layer that includes a first wireless power transfer (WPT) device, a first chip electrically connected to the first circuit layer, and a first tracking circuit disposed in the first chip. The first WPT device may be configured to extract energy from an electromagnetic signal and provide an output voltage. The first tracking circuit may be powered by the output voltage of the first WPT device and may output tracking data in response to an instruction extracted from the electromagnetic signal.Type: GrantFiled: September 9, 2020Date of Patent: July 12, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Min-Jer Wang, Ching-Nen Peng, Chewn-Pu Jou, Feng Wei Kuo, Hao Chen, Hung-Chih Lin, Huan-Neng Chen, Kuang-Kai Yen, Ming-Chieh Liu, Tsung-Hsiung Lee
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Patent number: 11340291Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.Type: GrantFiled: June 25, 2020Date of Patent: May 24, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Mill-Jer Wang, Kuo-Chuan Liu, Ching-Nen Peng, Hung-Chih Lin, Hao Chen
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Patent number: 11249112Abstract: A testing apparatus with reduced warping of the probe card and a method of reducing warping of a probe card of a testing apparatus are disclosed. The testing apparatus can include a testing head and a platform opposite the testing head, where the testing head and platform move relative to one another to bring a sample into contact with probing tips of the testing apparatus. The testing head can include a probe card printed circuit board, a stiffener, a discontinuous backer and a plurality of probing tips. The stiffener can be coupled to and reinforcing the probe card. The discontinuous backer can extend from the probe card to the stiffener, and can include at least one unfilled void extending from the stiffener to the probe card. The plurality of probing tips can extend from a distal end of the testing head.Type: GrantFiled: July 20, 2020Date of Patent: February 15, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Wei-Hsun Lin, Sen-Kuei Hsu, De-Jian Liu
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Patent number: 11231453Abstract: Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment.Type: GrantFiled: May 4, 2020Date of Patent: January 25, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Hao Chen, Mincent Lee
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Patent number: 11229109Abstract: The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.Type: GrantFiled: April 17, 2020Date of Patent: January 18, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Hao Cheng
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Publication number: 20210080487Abstract: A circuit probe includes a shielding probe having a base and a conductive probe ring on the base. A shielding cage is attached to the conductive probe ring and has an interior. The shielding cage is configured to be positioned to contain in the interior of the shielding cage at least one integrated circuit formed on a wafer, and to provide electromagnetic shielding of the at least one integrated circuit during testing of the at least one integrated circuit.Type: ApplicationFiled: September 16, 2019Publication date: March 18, 2021Inventors: Ching-Nen Peng, Hsien-Tang Wang, Mill-Jer Wang, Chi-Chang Lai
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Publication number: 20210013748Abstract: An integrated circuit (IC) includes a first circuit layer that includes a first wireless power transfer (WPT) device, a first chip electrically connected to the first circuit layer, and a first tracking circuit disposed in the first chip. The first WPT device may be configured to extract energy from an electromagnetic signal and provide an output voltage. The first tracking circuit may be powered by the output voltage of the first WPT device and may output tracking data in response to an instruction extracted from the electromagnetic signal.Type: ApplicationFiled: September 9, 2020Publication date: January 14, 2021Inventors: MIN-JER WANG, CHING-NEN PENG, CHEWN-PU JOU, FENG WEI KUO, HAO CHEN, HUNG-CHIH LIN, HUAN-NENG CHEN, KUANG-KAI YEN, MING-CHIEH LIU, TSUNG-HSIUNG LEE
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Publication number: 20200355737Abstract: A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.Type: ApplicationFiled: July 27, 2020Publication date: November 12, 2020Inventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Chuan-Ching Wang, Hao Chen
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Publication number: 20200348341Abstract: A testing apparatus with reduced warping of the probe card and a method of reducing warping of a probe card of a testing apparatus are disclosed. The testing apparatus can include a testing head and a platform opposite the testing head, where the testing head and platform move relative to one another to bring a sample into contact with probing tips of the testing apparatus. The testing head can include a probe card printed circuit board, a stiffener, a discontinuous backer and a plurality of probing tips. The stiffener can be coupled to and reinforcing the probe card. The discontinuous backer can extend from the probe card to the stiffener, and can include at least one unfilled void extending from the stiffener to the probe card. The plurality of probing tips can extend from a distal end of the testing head.Type: ApplicationFiled: July 20, 2020Publication date: November 5, 2020Inventors: Mill-Jer WANG, Ching-Nen PENG, Hung-Chih LIN, Wei-Hsun LIN, Sen-Kuei HSU, De-Jian LIU
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Publication number: 20200326370Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.Type: ApplicationFiled: June 25, 2020Publication date: October 15, 2020Inventors: Mill-Jer WANG, Kuo-Chuan LIU, Ching-Nen PENG, Hung-Chih LIN, Hao CHEN
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Patent number: 10790707Abstract: An integrated circuit (IC) includes a first circuit layer that includes a first wireless power transfer (WPT) device, a first chip electrically connected to the first circuit layer, and a first tracking circuit disposed in the first chip. The first WPT device may be configured to extract energy from an electromagnetic signal and provide an output voltage. The first tracking circuit may be powered by the output voltage of the first WPT device and may output tracking data in response to an instruction extracted from the electromagnetic signal.Type: GrantFiled: December 14, 2018Date of Patent: September 29, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Min-Jer Wang, Ching-Nen Peng, Chewn-Pu Jou, Feng Wei Kuo, Hao Chen, Hung-Chih Lin, Huan-Neng Chen, Kuang-Kai Yen, Ming-Chieh Liu, Tsung-Hsiung Lee
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Publication number: 20200264227Abstract: Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment.Type: ApplicationFiled: May 4, 2020Publication date: August 20, 2020Inventors: Mill-Jer WANG, Ching-Nen PENG, Hung-Chih LIN, Hao CHEN, Mincent LEE
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Publication number: 20200245439Abstract: The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.Type: ApplicationFiled: April 17, 2020Publication date: July 30, 2020Inventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Hao Cheng
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Patent number: 10725090Abstract: A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.Type: GrantFiled: February 9, 2018Date of Patent: July 28, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Chuan-Ching Wang, Hao Chen