Patents by Inventor Ching-Pei Hsieh
Ching-Pei Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230060956Abstract: A method of forming a semiconductor device structure includes forming a resist structure over a substrate, the resist structure includes an anti-reflective coating (ARC) layer and a photoresist layer over the ARC layer. The method further includes patterning the photoresist layer to form a trench therein. The method further includes performing a hydrogen plasma treatment to the patterned photoresist layer, wherein the hydrogen plasma treatment is configured to smooth sidewalls of the trench, and the hydrogen plasma treatment is performed at a temperature ranging from about 200° C. to about 600° C. The method further includes patterning the ARC layer using the patterned photoresist layer as a etch mask.Type: ApplicationFiled: November 10, 2022Publication date: March 2, 2023Inventors: Sheng-Lin HSIEH, I-Chih CHEN, Ching-Pei HSIEH, Kuan Jung CHEN
-
Patent number: 11527406Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a resist structure over a substrate. The resist structure includes an anti-reflective coating (ARC) layer and a photoresist layer over the ARC layer. The method further includes patterning the photoresist layer to form a trench therein. The method further includes performing a hydrogen plasma treatment to the patterned photoresist layer. The hydrogen plasma treatment is configured to smooth sidewalls of the trench without etching the ARC layer. The method further includes patterning the ARC layer using the patterned photoresist layer as a etch mask.Type: GrantFiled: January 14, 2020Date of Patent: December 13, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITEDInventors: Sheng-Lin Hsieh, I-Chih Chen, Ching-Pei Hsieh, Kuan Jung Chen
-
Publication number: 20210183644Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a resist structure over a substrate. The resist structure includes an anti-reflective coating (ARC) layer and a photoresist layer over the ARC layer. The method further includes patterning the photoresist layer to form a trench therein. The method further includes performing a hydrogen plasma treatment to the patterned photoresist layer. The hydrogen plasma treatment is configured to smooth sidewalls of the trench without etching the ARC layer. The method further includes patterning the ARC layer using the patterned photoresist layer as a etch mask.Type: ApplicationFiled: January 14, 2020Publication date: June 17, 2021Inventors: Sheng-Lin HSIEH, I-Chih CHEN, Ching-Pei HSIEH, Kuan Jung CHEN
-
Patent number: 11018299Abstract: A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.Type: GrantFiled: December 13, 2019Date of Patent: May 25, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Fu-Ting Sung, Shih-Chang Liu
-
Patent number: 10957852Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.Type: GrantFiled: April 20, 2020Date of Patent: March 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fu-Ting Sung, Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Shih-Chang Liu
-
Publication number: 20200251653Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.Type: ApplicationFiled: April 20, 2020Publication date: August 6, 2020Inventors: Fu-Ting Sung, Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Shih-Chang Liu
-
Patent number: 10629811Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.Type: GrantFiled: December 18, 2018Date of Patent: April 21, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fu-Ting Sung, Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Shih-Chang Liu
-
Publication number: 20200119272Abstract: A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.Type: ApplicationFiled: December 13, 2019Publication date: April 16, 2020Inventors: Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Fu-Ting Sung, Shih-Chang Liu
-
Patent number: 10516107Abstract: A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.Type: GrantFiled: December 12, 2018Date of Patent: December 24, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Fu-Ting Sung, Shih-Chang Liu
-
Patent number: 10483322Abstract: A memory device includes a first inter-layer dielectric layer, plural conductive features, plural memory structures, a filler, and a second inter-layer dielectric layer. The conductive features are embedded in the first inter-layer dielectric layer. The memory structures are respectively over the conductive features. The filler is in between the memory structures. The second inter-layer dielectric layer is over the filler and the memory structures, and the second inter-layer dielectric layer and the filler form an interface, in which the interface extends from one of the memory structures to another of the memory structures.Type: GrantFiled: June 8, 2017Date of Patent: November 19, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ching-Pei Hsieh, Hsia-Wei Chen, Yu-Wen Liao
-
Publication number: 20190148638Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.Type: ApplicationFiled: December 18, 2018Publication date: May 16, 2019Inventors: Fu-Ting Sung, Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Shih-Chang Liu
-
Publication number: 20190115531Abstract: A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.Type: ApplicationFiled: December 12, 2018Publication date: April 18, 2019Inventors: Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Fu-Ting Sung, Shih-Chang Liu
-
Patent number: 10164184Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.Type: GrantFiled: November 6, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fu-Ting Sung, Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Shih-Chang Liu
-
Patent number: 10164183Abstract: A semiconductor device includes at least one bottom electrode, a resistive layer, and a top electrode. The bottom electrode has two opposite sidewalls. The resistive layer is disposed on the bottom electrode, extends past at least one of the two opposite sidewalls of the at least one bottom electrode, and has a variable resistance. The resistive layer is disposed on the bottom electrode and extends past at least one of the two opposite sidewalls of the at least one bottom electrode.Type: GrantFiled: January 30, 2017Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Yen Chou, Ching-Pei Hsieh
-
Patent number: 10158073Abstract: The present disclosure provides a manufacturing method for the semiconductor structure, including forming a bottom metal layer including copper, forming a planar memory layer over the bottom metal layer, forming an electrode over the planar memory layer by a self-aligning operation, and defining a memory cell by patterning the planar memory layer.Type: GrantFiled: April 10, 2017Date of Patent: December 18, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chung-Yen Chou, Ching-Pei Hsieh, Shih-Chang Liu
-
Patent number: 10158069Abstract: A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.Type: GrantFiled: November 20, 2017Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Fu-Ting Sung, Shih-Chang Liu
-
Publication number: 20180358409Abstract: A memory device includes a first inter-layer dielectric layer, plural conductive features, plural memory structures, a filler, and a second inter-layer dielectric layer. The conductive features are embedded in the first inter-layer dielectric layer. The memory structures are respectively over the conductive features. The filler is in between the memory structures. The second inter-layer dielectric layer is over the filler and the memory structures, and the second inter-layer dielectric layer and the filler form an interface, in which the interface extends from one of the memory structures to another of the memory structures.Type: ApplicationFiled: June 8, 2017Publication date: December 13, 2018Inventors: Ching-Pei HSIEH, Hsia-Wei CHEN, Yu-Wen LIAO
-
Publication number: 20180151799Abstract: A semiconductor device includes at least one bottom electrode, a resistive layer, and a top electrode. The bottom electrode has two opposite sidewalls. The resistive layer is disposed on the bottom electrode, extends past at least one of the two opposite sidewalls of the at least one bottom electrode, and has a variable resistance. The resistive layer is disposed on the bottom electrode and extends past at least one of the two opposite sidewalls of the at least one bottom electrode.Type: ApplicationFiled: January 30, 2017Publication date: May 31, 2018Inventors: Chung-Yen Chou, Ching-Pei Hsieh
-
Publication number: 20180090680Abstract: A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.Type: ApplicationFiled: November 20, 2017Publication date: March 29, 2018Inventors: Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Fu-Ting Sung, Shih-Chang Liu
-
Publication number: 20180062074Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.Type: ApplicationFiled: November 6, 2017Publication date: March 1, 2018Inventors: Fu-Ting Sung, Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Shih-Chang Liu