Patents by Inventor Ching-Pei Hsieh
Ching-Pei Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9853091Abstract: The present disclosure relates to an integrated circuits device having an RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a lower metal interconnect line disposed within a lower inter-level dielectric (ILD) layer and an upper metal interconnect line disposed within an upper inter-level dielectric (ILD) layer. The integrated circuit device also has a memory cell array disposed between the lower metal interconnect line and the upper metal interconnect line, including memory cells arranged in rows and columns, the memory cells respectively includes a bottom electrode and a top electrode separated by a RRAM dielectric having a variable resistance. A bottom contact structure is disposed on the lower metal interconnect line and along sidewalls of the bottom electrode, electrically coupling the lower metal interconnect line and the bottom electrode.Type: GrantFiled: April 26, 2016Date of Patent: December 26, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Yen Chou, Ching-Pei Hsieh, Chia-Shiung Tsai, Shih-Chang Liu
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Patent number: 9837605Abstract: A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.Type: GrantFiled: August 16, 2013Date of Patent: December 5, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Pei Hsieh, Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
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Patent number: 9837606Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.Type: GrantFiled: August 15, 2016Date of Patent: December 5, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fu-Ting Sung, Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Shih-Chang Liu
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Patent number: 9825224Abstract: The present disclosure relates to an integrated circuit device having an RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a bottom electrode disposed over a lower metal interconnect layer. The integrated circuit device also has a resistance switching layer with a variable resistance located on the bottom electrode, and a top electrode located over the resistance switching layer. The integrated circuit device also has a self-sputtering spacer having a lateral portion that surrounds the bottom electrode at a position that is vertically disposed between the resistance switching layer and a bottom etch stop layer and a vertical portion abutting sidewalls of the resistance switching layer and the top electrode. The integrated circuit device also has a top etch stop layer located over the bottom etch stop layer abutting sidewalls of the self-sputtering spacer and overlying the top electrode.Type: GrantFiled: August 10, 2016Date of Patent: November 21, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Pei Hsieh, Chung-Yen Chou, Shih-Chang Liu
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Publication number: 20170309682Abstract: The present disclosure relates to an integrated circuits device having an RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a lower metal interconnect line disposed within a lower inter-level dielectric (ILD) layer and an upper metal interconnect line disposed within an upper inter-level dielectric (ILD) layer. The integrated circuit device also has a memory cell array disposed between the lower metal interconnect line and the upper metal interconnect line, including memory cells arranged in rows and columns, the memory cells respectively includes a bottom electrode and a top electrode separated by a RRAM dielectric having a variable resistance. A bottom contact structure is disposed on the lower metal interconnect line and along sidewalls of the bottom electrode, electrically coupling the lower metal interconnect line and the bottom electrode.Type: ApplicationFiled: April 26, 2016Publication date: October 26, 2017Inventors: Chung-Yen Chou, Ching-Pei Hsieh, Chia-Shiung Tsai, Shih-Chang Liu
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Publication number: 20170229646Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer, a planar bottom barrier layer over and in contact with the Nth metal layer, a data storage layer over the planar bottom barrier layer, an electrode over the data storage layer, and an (N+1)th metal layer over the electrode. N is a positive integer. A manufacturing method for the semiconductor structure is also provided.Type: ApplicationFiled: April 10, 2017Publication date: August 10, 2017Inventors: CHUNG-YEN CHOU, CHING-PEI HSIEH, SHIH-CHANG LIU
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Patent number: 9653682Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer, a planar bottom barrier layer over and in contact with the Nth metal layer, a data storage layer over the planar bottom barrier layer, an electrode over the data storage layer, and an (N+1)th metal layer over the electrode. N is a positive integer. A manufacturing method for the semiconductor structure is also provided.Type: GrantFiled: February 5, 2016Date of Patent: May 16, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chung-Yen Chou, Ching-Pei Hsieh, Shih-Chang Liu
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Patent number: 9620582Abstract: The present disclosure relates a metal-insulator-metal (MIM) capacitor. In some embodiments, the MIM capacitor has a capacitor bottom metal (CBM) electrode arranged over a semiconductor substrate. The MIM capacitor has a high-k dielectric disposed over the CBM electrode and a capacitor top metal (CTM) electrode arranged over the high-k dielectric layer. The MIM capacitor has a dummy structure that is disposed vertically over the high-k dielectric layer and laterally apart from the CTM electrode. The dummy structure includes a conductive body having a same material as the CTM electrode.Type: GrantFiled: January 27, 2015Date of Patent: April 11, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Pei Hsieh, Chern-Yow Hsu, Shih-Chang Liu
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Publication number: 20160351803Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.Type: ApplicationFiled: August 15, 2016Publication date: December 1, 2016Inventors: Fu-Ting Sung, Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Shih-Chang Liu
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Publication number: 20160351806Abstract: The present disclosure relates to an integrated circuit device having an RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a bottom electrode disposed over a lower metal interconnect layer. The integrated circuit device also has a resistance switching layer with a variable resistance located on the bottom electrode, and a top electrode located over the resistance switching layer. The integrated circuit device also has a self-sputtering spacer having a lateral portion that surrounds the bottom electrode at a position that is vertically disposed between the resistance switching layer and a bottom etch stop layer and a vertical portion abutting sidewalls of the resistance switching layer and the top electrode. The integrated circuit device also has a top etch stop layer located over the bottom etch stop layer abutting sidewalls of the self-sputtering spacer and overlying the top electrode.Type: ApplicationFiled: August 10, 2016Publication date: December 1, 2016Inventors: Ching-Pei Hsieh, Chung-Yen Chou, Shih-Chang Liu
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Patent number: 9466794Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a non-planar portion, a resistive material layer conformally covering the non-planar portion of the bottom electrode; and, a top electrode on the resistive material layer. The via portion of the bottom electrode is embedded in a first RRAM stop layer. The non-planar portion of the bottom electrode has an apex and is centered above the via portion.Type: GrantFiled: January 4, 2016Date of Patent: October 11, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Chieh Yang, Wen-Ting Chu, Yu-Wen Liao, Chih-Yang Chang, Hsia-Wei Chen, Kuo-Chi Tu, Ching-Pei Hsieh
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Patent number: 9431603Abstract: The present disclosure relates to an integrated circuit device having an RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a bottom electrode disposed over a lower metal interconnect layer. The integrated circuit device also has a resistance switching layer with a variable resistance located on the bottom electrode, and a top electrode located over the resistance switching layer. The integrated circuit device also has a spacer having a lateral portion that surrounds the bottom electrode at a position that is vertically disposed between the resistance switching layer and a bottom etch stop layer and a vertical portion abutting sidewalls of the resistance switching layer and the top electrode. The integrated circuit device also has a top etch stop layer located over the bottom etch stop layer abutting sidewalls of the spacer and overlying the top electrode.Type: GrantFiled: May 15, 2015Date of Patent: August 30, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Pei Hsieh, Chung-Yen Chou, Shih-Chang Liu
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Patent number: 9419218Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.Type: GrantFiled: May 24, 2015Date of Patent: August 16, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fu-Ting Sung, Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Shih-Chang Liu
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Patent number: 9406883Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first electrode over the semiconductor substrate. The first electrode has a ring-shaped cross section. The semiconductor device structure also includes a resistance-switching layer over the first electrode and a second electrode over the resistance-switching layer.Type: GrantFiled: January 8, 2015Date of Patent: August 2, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Ching-Pei Hsieh, Chern-Yow Hsu, Shih-Chang Liu
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Publication number: 20160218172Abstract: The present disclosure relates a metal-insulator-metal (MIM) capacitor. In some embodiments, the MIM capacitor has a capacitor bottom metal (CBM) electrode arranged over a semiconductor substrate. The MIM capacitor has a high-k dielectric disposed over the CBM electrode and a capacitor top metal (CTM) electrode arranged over the high-k dielectric layer. The MIM capacitor has a dummy structure that is disposed vertically over the high-k dielectric layer and laterally apart from the CTM electrode. The dummy structure includes a conductive body having a same material as the CTM electrode.Type: ApplicationFiled: January 27, 2015Publication date: July 28, 2016Inventors: Ching-Pei Hsieh, Chern-Yow Hsu, Shih-Chang Liu
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Publication number: 20160204344Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first electrode over the semiconductor substrate. The first electrode has a ring-shaped cross section. The semiconductor device structure also includes a resistance-switching layer over the first electrode and a second electrode over the resistance-switching layer.Type: ApplicationFiled: January 8, 2015Publication date: July 14, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Ching-Pei HSIEH, Chern-Yow HSU, Shih-Chang LIU
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Publication number: 20160118584Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a non-planar portion, a resistive material layer conformally covering the non-planar portion of the bottom electrode; and, a top electrode on the resistive material layer. The via portion of the bottom electrode is embedded in a first RRAM stop layer. The non-planar portion of the bottom electrode has an apex and is centered above the via portion.Type: ApplicationFiled: January 4, 2016Publication date: April 28, 2016Inventors: Chin-Chieh Yang, Wen-Ting Chu, Yu-Wen Liao, Chih-Yang Chang, Hsia-Wei Chen, Kuo-Chi Tu, Ching-Pei Hsieh
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Patent number: 9299927Abstract: A manufacture includes a first electrode having an upper surface, a second electrode having a lower surface directly over the upper surface of the first electrode, a resistance variable film between the first electrode and the second electrode, and a first conductive member on and surrounding an upper portion of the second electrode.Type: GrantFiled: August 16, 2013Date of Patent: March 29, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Pei Hsieh, Yu-Hsing Chang, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
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Patent number: 9231205Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a non-planar portion, a resistive material layer conformally covering the non-planar portion of the bottom electrode; and, a top electrode on the resistive material layer. The via portion of the bottom electrode is embedded in a first RRAM stop layer. The non-planar portion of the bottom electrode has an apex and is centered above the via portion.Type: GrantFiled: March 13, 2013Date of Patent: January 5, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Chieh Yang, Wen-Ting Chu, Yu-Wen Liao, Chih-Yang Chang, Hsia-Wei Chen, Kuo-Chi Tu, Ching-Pei Hsieh
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Publication number: 20150255713Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.Type: ApplicationFiled: May 24, 2015Publication date: September 10, 2015Inventors: Fu-Ting Sung, Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Shih-Chang Liu