Abstract: The present disclosure provides methods of making resistive random access memory (RRAM) cells. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode, a first spacer surrounding the capping layer and a top electrode, a second spacer surround the top portion of the bottom electrode and the first spacer, and the top electrode. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer.

Abstract: The present disclosure provides methods of making resistive random access memory (RRAM) cells. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode, a first spacer surrounding the capping layer and a top electrode, a second spacer surround the top portion of the bottom electrode and the first spacer, and the top electrode. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer.

Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.

Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.

Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode, a first spacer surrounding the capping layer and a top electrode, a second spacer surround the top portion of the bottom electrode and the first spacer, and the top electrode. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer.

Abstract: A manufacture includes a first electrode having an upper surface, a second electrode having a lower surface directly over the upper surface of the first electrode, a resistance variable film between the first electrode and the second electrode, and a first conductive member on and surrounding an upper portion of the second electrode.

Abstract: A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.

Abstract: A memory cell and method includes a first electrode formed in an opening in a first dielectric layer, the first dielectric layer being formed on a substrate including a metal layer, the opening being configured to allow physical contact between the first electrode and the metal layer, the first electrode having a first width W1 and extending a distance beyond a region defined by the opening, a resistive layer formed on the first electrode and having substantially the first width W1, a capping layer, having a second width W2 less than the first width W1, formed on the resistive layer, a second electrode formed on the capping layer and having substantially the second width W2, a first composite spacer region having at least two different dielectric layers formed on the resistive layer between the first width W1 and the second width W2, and a via coupled to the second electrode.