Patents by Inventor Ching-Sen Kuo
Ching-Sen Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230402315Abstract: Double patterning techniques described herein may reduce corner rounding, etch loading, and/or other defects that might otherwise arise during formation of a deep trench isolation (DTI) structure in a pixel array. The double patterning techniques include forming a first set of trenches in a first direction and forming a second set of trenches in a second direction in a plurality of patterning operations such that minimal to no etch loading and/or corner rounding is present at and/or near the intersections of the first set of trenches and the second set of trenches.Type: ApplicationFiled: August 10, 2023Publication date: December 14, 2023Inventors: Wei-Chao CHIU, Yu-Wen CHEN, Yong-Jin LIOU, Chun-Wei CHANG, Ching-Sen KUO, Feng-Jia SHIU
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Publication number: 20230386820Abstract: Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.Type: ApplicationFiled: July 24, 2023Publication date: November 30, 2023Inventors: Wei-Lin CHANG, Chih-Chien WANG, Chihy-Yuan CHENG, Sz-Fan CHIEN, Chien-Hung LIN, Chun-Chang CHEN, Ching-Sen KUO, Feng-Jia SHIU
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Patent number: 11769662Abstract: Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.Type: GrantFiled: March 19, 2021Date of Patent: September 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Lin Chang, Chih-Chien Wang, Chihy-Yuan Cheng, Sz-Fan Chen, Chien-Hung Lin, Chun-Chang Chen, Ching-Sen Kuo, Feng-Jia Shiu
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Publication number: 20230290637Abstract: Implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. The pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. Then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. In this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.Type: ApplicationFiled: May 12, 2023Publication date: September 14, 2023Inventors: Wei-Chao CHIU, Yong-Jin LIOU, Yu-Wen CHEN, Chun-Wei CHANG, Ching-Sen KUO, Feng-Jia SHIU
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Patent number: 11665897Abstract: A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer.Type: GrantFiled: March 14, 2022Date of Patent: May 30, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Chang Wu, Chihy-Yuan Cheng, Sz-Fan Chen, Shun-Shing Yang, Wei-Lin Chang, Ching-Sen Kuo, Feng-Jia Shiu, Chun-Chang Chen
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Patent number: 11658031Abstract: Implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. The pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. Then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. In this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.Type: GrantFiled: June 1, 2021Date of Patent: May 23, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chao Chiu, Yong-Jin Liou, Yu-Wen Chen, Chun-Wei Chang, Ching-Sen Kuo, Feng-Jia Shiu
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Publication number: 20220359588Abstract: A method includes performing a first lithography process using a first pattern of a first photomask to form a first photoresist pattern on a front side of a device substrate; performing a first implantation process using the first pattern as a mask to form first isolation regions in the device substrate; after performing the first implantation process, performing a second lithography process using a second pattern of a second photomask to form a second photoresist pattern on the front side of the device substrate, the second pattern being shifted from the first pattern by a distance less than the first pitch and in the first direction; performing a second implantation process using the second photoresist pattern as a mask to form second isolation regions in the device substrate and spaced apart from the first isolation regions; and forming pixels between the first and second isolation regions.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Chao CHIU, Chun-Wei CHANG, Ching-Sen KUO, Feng-Jia SHIU
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Publication number: 20220301849Abstract: Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.Type: ApplicationFiled: March 19, 2021Publication date: September 22, 2022Inventors: Wei-Lin CHANG, Chih-Chien WANG, Chihy-Yuan CHENG, Sz-Fan CHEN, Chien-Hung LIN, Chun-Chang CHEN, Ching-Sen KUO, Feng-Jia SHIU
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Publication number: 20220285155Abstract: Implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. The pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. Then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. In this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.Type: ApplicationFiled: June 1, 2021Publication date: September 8, 2022Inventors: Wei-Chao CHIU, Yong-Jin LIOU, Yu-Wen CHEN, Chun-Wei CHANG, Ching-Sen KUO, Feng-Jia SHIU
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Publication number: 20220285203Abstract: Double patterning techniques described herein may reduce corner rounding, etch loading, and/or other defects that might otherwise arise during formation of a deep trench isolation (DTI) structure in a pixel array. The double patterning techniques include forming a first set of trenches in a first direction and forming a second set of trenches in a second direction in a plurality of patterning operations such that minimal to no etch loading and/or corner rounding is present at and/or near the intersections of the first set of trenches and the second set of trenches.Type: ApplicationFiled: June 1, 2021Publication date: September 8, 2022Inventors: Wei-Chao CHIU, Yu-Wen CHEN, Yong-Jin LIOU, Chun-Wei CHANG, Ching-Sen KUO, Feng-Jia SHIU
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Patent number: 11411033Abstract: A method includes forming a first photoresist layer on a front side of a device substrate and having first trenches spaced apart from each other. A first implantation process is performed using the first photoresist layer as a mask to form first isolation regions in the device substrate. A second photoresist layer is formed on the front side and has second trenches. A second implantation process is performed using the second photoresist layer as a mask to form second isolation regions in the device substrate and crossing over the first isolation regions. A third photoresist layer is formed on the front side and has third trenches spaced apart from each other. A third implantation process is performed using the third photoresist layer as a mask to form third isolation regions in the device substrate and crossing over the first isolation regions but spaced apart from the second isolation regions.Type: GrantFiled: March 13, 2020Date of Patent: August 9, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Chao Chiu, Chun-Wei Chang, Ching-Sen Kuo, Feng-Jia Shiu
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Publication number: 20220199636Abstract: A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer.Type: ApplicationFiled: March 14, 2022Publication date: June 23, 2022Inventors: Chun-Chang Wu, Chihy-Yuan Cheng, Sz-Fan Chen, Shun-Shing Yang, Wei-Lin Chang, Ching-Sen Kuo, Feng-Jia Shiu, Chun-Chang Chen
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Patent number: 11276699Abstract: A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer.Type: GrantFiled: December 19, 2019Date of Patent: March 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Chang Wu, Chihy-Yuan Cheng, Sz-Fan Chen, Shun-Shing Yang, Wei-Lin Chang, Ching-Sen Kuo, Feng-Jia Shiu, Chun-Chang Chen
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Publication number: 20210327748Abstract: In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.Type: ApplicationFiled: June 28, 2021Publication date: October 21, 2021Inventors: Tsai-Ming HUANG, Wei-Chieh HUANG, Hsun-Chung KUANG, Yen-Chang CHU, Cheng-Che CHUNG, Chin-Wei LIANG, Ching-Sen KUO, Jieh-Jang CHEN, Feng-Jia SHIU, Sheng-Chau CHEN
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Patent number: 11086221Abstract: A first photoresist pattern and a second photoresist pattern are formed over a substrate. The first photoresist pattern is separated from the second photoresist pattern by a gap. A chemical mixture is coated on the first and second photoresist patterns. The chemical mixture contains a chemical material and surfactant particles mixed into the chemical material. The chemical mixture fills the gap. A baking process is performed on the first and second photoresist patterns, the baking process causing the gap to shrink. At least some surfactant particles are disposed at sidewall boundaries of the gap. A developing process is performed on the first and second photoresist patterns. The developing process removes the chemical mixture in the gap and over the photoresist patterns. The surfactant particles disposed at sidewall boundaries of the gap reduce a capillary effect during the developing process.Type: GrantFiled: August 3, 2020Date of Patent: August 10, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Chao Chiu, Chih-Chien Wang, Feng-Jia Shiu, Ching-Sen Kuo, Chun-Wei Chang, Kai Tzeng
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Patent number: 11049767Abstract: In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.Type: GrantFiled: September 26, 2019Date of Patent: June 29, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsai-Ming Huang, Wei-Chieh Huang, Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Che Chung, Chin-Wei Liang, Ching-Sen Kuo, Jieh-Jang Chen, Feng-Jia Shiu, Sheng-Chau Chen
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Publication number: 20210193705Abstract: A method includes forming a first photoresist layer on a front side of a device substrate and having first trenches spaced apart from each other. A first implantation process is performed using the first photoresist layer as a mask to form first isolation regions in the device substrate. A second photoresist layer is formed on the front side and has second trenches. A second implantation process is performed using the second photoresist layer as a mask to form second isolation regions in the device substrate and crossing over the first isolation regions. A third photoresist layer is formed on the front side and has third trenches spaced apart from each other. A third implantation process is performed using the third photoresist layer as a mask to form third isolation regions in the device substrate and crossing over the first isolation regions but spaced apart from the second isolation regions.Type: ApplicationFiled: March 13, 2020Publication date: June 24, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Chao CHIU, Chun-Wei CHANG, Ching-Sen KUO, Feng-Jia SHIU
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Patent number: 10943783Abstract: In a method of manufacturing a semiconductor device, a first layer having an opening is formed over a substrate. A second layer is formed over the first layer and the substrate. A photo resist pattern is formed over the second layer above the opening of the first layer. The photo resist pattern is reflowed by a thermal process. An etch-back operation is performed to planarize the second layer.Type: GrantFiled: May 30, 2019Date of Patent: March 9, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Che Chung, Yi Jen Tsai, Ching-Sen Kuo, Tsai-Ming Huang, Jieh-Jang Chen, Feng-Jia Shiu
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Patent number: 10910260Abstract: A method for manufacturing a semiconductor device includes forming a structure protruding from a substrate, forming a dielectric layer covering the structure, forming a dummy layer covering the dielectric layer, and performing a planarization process to completely remove the dummy layer. A material of the dummy layer has a slower removal rate to the planarization process than a material of the dielectric layer.Type: GrantFiled: October 25, 2019Date of Patent: February 2, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Chieh Huang, Chin-Wei Liang, Feng-Jia Shiu, Hsia-Wei Chen, Jieh-Jang Chen, Ching-Sen Kuo
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Publication number: 20200365645Abstract: A first photoresist pattern and a second photoresist pattern are formed over a substrate. The first photoresist pattern is separated from the second photoresist pattern by a gap. A chemical mixture is coated on the first and second photoresist patterns. The chemical mixture contains a chemical material and surfactant particles mixed into the chemical material. The chemical mixture fills the gap. A baking process is performed on the first and second photoresist patterns, the baking process causing the gap to shrink. At least some surfactant particles are disposed at sidewall boundaries of the gap. A developing process is performed on the first and second photoresist patterns. The developing process removes the chemical mixture in the gap and over the photoresist patterns. The surfactant particles disposed at sidewall boundaries of the gap reduce a capillary effect during the developing process.Type: ApplicationFiled: August 3, 2020Publication date: November 19, 2020Inventors: Wei-Chao Chiu, Chih-Chien Wang, Feng-Jia Shiu, Ching-Sen Kuo, Chun-Wei Chang, Kai Tzeng