Patents by Inventor Ching-Sen Kuo
Ching-Sen Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170186808Abstract: A first photoresist pattern and a second photoresist pattern are formed over a substrate. The first photoresist pattern is separated from the second photoresist pattern by a gap. A chemical mixture is coated on the first and second photoresist patterns. The chemical mixture contains a chemical material and surfactant particles mixed into the chemical material. The chemical mixture fills the gap. A baking process is performed on the first and second photoresist patterns, the baking process causing the gap to shrink. At least some surfactant particles are disposed at sidewall boundaries of the gap. A developing process is performed on the first and second photoresist patterns. The developing process removes the chemical mixture in the gap and over the photoresist patterns. The surfactant particles disposed at sidewall boundaries of the gap reduce a capillary effect during the developing process.Type: ApplicationFiled: March 7, 2016Publication date: June 29, 2017Inventors: Wei-Chao Chiu, Chih-Chien Wang, Feng-Jia Shiu, Ching-Sen Kuo, Chun-Wei Chang, Kai Tzeng
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Patent number: 9437650Abstract: A method of forming of an image sensor device includes a patterned hardmask layer is formed over a substrate. The patterned hard mask layer has a plurality of first openings in a periphery region, and a plurality of second openings in a pixel region. A first patterned mask layer is formed over the pixel region to expose the periphery region. A plurality of first trenches is etched into the substrate in the periphery region. Each first trench, each first opening and each second opening are filled with a dielectric material. A second patterned mask layer is formed over the periphery region to expose the pixel region. The dielectric material in each second opening over the pixel region is removed. A plurality of dopants is implanted through each second opening to form various doped isolation features in the pixel region.Type: GrantFiled: May 26, 2015Date of Patent: September 6, 2016Assignee: Taiwam Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chen Lu, Ching-Sen Kuo, Shih-Chi Fu, Ming-Ying Hsieh
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Publication number: 20150255503Abstract: A method of forming of an image sensor device includes a patterned hardmask layer is formed over a substrate. The patterned hard mask layer has a plurality of first openings in a periphery region, and a plurality of second openings in a pixel region. A first patterned mask layer is formed over the pixel region to expose the periphery region. A plurality of first trenches is etched into the substrate in the periphery region. Each first trench, each first opening and each second opening are filled with a dielectric material. A second patterned mask layer is formed over the periphery region to expose the pixel region. The dielectric material in each second opening over the pixel region is removed. A plurality of dopants is implanted through each second opening to form various doped isolation features in the pixel region.Type: ApplicationFiled: May 26, 2015Publication date: September 10, 2015Inventors: Wen-Chen Lu, Ching-Sen Kuo, Shih-Chi Fu, Ming-Ying Hsieh
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Patent number: 9040341Abstract: A method of forming of an image sensor device includes a patterned hardmask layer is formed over a substrate. The patterned hard mask layer has a plurality of first openings in a periphery region, and a plurality of second openings in a pixel region. A first patterned mask layer is formed over the pixel region to expose the periphery region. A plurality of first trenches is etched into the substrate in the periphery region. Each first trench, each first opening and each second opening are filled with a dielectric material. A second patterned mask layer is formed over the periphery region to expose the pixel region. The dielectric material in each second opening over the pixel region is removed. A plurality of dopants is implanted through each second opening to form various doped isolation features in the pixel region.Type: GrantFiled: June 4, 2012Date of Patent: May 26, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chen Lu, Ching-Sen Kuo, Shih-Chi Fu, Ming-Ying Hsieh
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Patent number: 8809172Abstract: Methods of forming self-aligned patterns for performing oppositely doped deep implantations in a semiconductor substrate are disclosed. The semiconductor substrate has implantation and non-implantation regions. The methods include forming a hardmask pattern for a first implantation with a first conductivity-type dopant, depositing an etch stop layer, filling trenches between the hardmask pattern with a sacrificial filler material having a higher wet etch resistance than the hardmask, removing a top portion of the sacrificial filler material and the etch stop layer over a top surface of the hardmask pattern, removing the hardmask pattern in the implantation region by wet etching, and performing a second ion implantation with a second conductivity type dopant opposite of the first conductivity type.Type: GrantFiled: March 15, 2013Date of Patent: August 19, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Yan Li, Shih-Chi Fu, Ching-Sen Kuo, Wen-Chen Lu
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Publication number: 20130323917Abstract: Methods of forming self-aligned patterns for performing oppositely doped deep implantations in a semiconductor substrate are disclosed. The semiconductor substrate has implantation and non-implantation regions. The methods include forming a hardmask pattern for a first implantation with a first conductivity-type dopant, depositing an etch stop layer, filling trenches between the hardmask pattern with a sacrificial filler material having a higher wet etch resistance than the hardmask, removing a top portion of the sacrificial filler material and the etch stop layer over a top surface of the hardmask pattern, removing the hardmask pattern in the implantation region by wet etching, and performing a second ion implantation with a second conductivity type dopant opposite of the first conductivity type.Type: ApplicationFiled: March 15, 2013Publication date: December 5, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Yan LI, Shih-Chi FU, Ching-Sen KUO, Wen-Chen LU
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Publication number: 20130323876Abstract: A method of forming of an image sensor device includes a patterned hardmask layer is formed over a substrate. The patterned hard mask layer has a plurality of first openings in a periphery region, and a plurality of second openings in a pixel region. A first patterned mask layer is formed over the pixel region to expose the periphery region. A plurality of first trenches is etched into the substrate in the periphery region. Each first trench, each first opening and each second opening are filled with a dielectric material. A second patterned mask layer is formed over the periphery region to expose the pixel region. The dielectric material in each second opening over the pixel region is removed. A plurality of dopants is implanted through each second opening to form various doped isolation features in the pixel region.Type: ApplicationFiled: June 4, 2012Publication date: December 5, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Chen Lu, Ching-Sen Kuo, Shih-Chi Fu, Ming-Ying Hsieh
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Patent number: 8587084Abstract: A sensor array is integrated onto the same chip as core logic. The sensor array uses a first polysilicon and the core logic uses a second polysilicon. The first polysilicon is etched to provide a tapered profile edge in the interface between the sensor array and the core logic regions to avoid an excessive step. Amorphous carbon can be deposited over the interface region without formation of voids, thus providing for improved manufacturing yield and reliability.Type: GrantFiled: January 2, 2012Date of Patent: November 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Chi Fu, Ching-Sen Kuo, Wen-Chen Lu, Chih-Yuan Chen
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Publication number: 20130168794Abstract: A sensor array is integrated onto the same chip as core logic. The sensor array uses a first polysilicon and the core logic uses a second polysilicon. The first polysilicon is etched to provide a tapered profile edge in the interface between the sensor array and the core logic regions to avoid an excessive step. Amorphous carbon can be deposited over the interface region without formation of voids, thus providing for improved manufacturing yield and reliability.Type: ApplicationFiled: January 2, 2012Publication date: July 4, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Chi Fu, Ching-Sen Kuo, Wen-Chen Lu, Chih-Yuan Chen
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Patent number: 7443005Abstract: An image sensor includes a double-microlens structure with an outer microlens aligned over an inner microlens, both microlenses aligned over a corresponding photosensor. The inner or outer microlens may be formed by a silylation process in which a reactive portion of a photoresist material reacts with a silicon-containing agent. The inner or outer microlens may be formed by step etching of a dielectric material, the step etching process including a series of alternating etch steps including an anisotropic etching step and an etching step that causes patterned photoresist to laterally recede. Subsequent isotropic etching processes may be used to smooth the etched step structure and form a smooth lens. A thermally stable and photosensitive polymeric/organic material may also be used to form permanent inner or outer lenses. The photosensitive material is coated then patterned using photolithography, reflowed, then cured to form a permanent lens structure.Type: GrantFiled: November 5, 2004Date of Patent: October 28, 2008Assignee: Tiawan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Sen Kuo, Feng-Jia Shiu, Gwo-Yuh Shiau, Jieh-Jang Chen, Shih-Chi Fu, Chien Hsien Tseng, Chia-Shiung Tsai, Yuan-Hung Liu, Yeur-Luen Tu, Chih-Ta Wu, Chi-Hsin Lo
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Patent number: 7189957Abstract: Described is a light-directing feature formed in the inter-level dielectric (ILD) layer in combination with an anti-reflective (AR) layer to effectively and simultaneously increase quantum efficiency and cross-talk immunity thereby improving photonic performances of photo-sensitive integrated circuits. A plurality of photosensor cells is formed on a semiconductor substrate. An AR layer is subsequently formed on the plurality of photosensor cells, the AR layer being substantially non-reflective of incident light. An ILD layer is then formed over the AR layer, the ILD layer comprising a plurality of light-directing features formed in openings in the ILD layer over the AR layer above and about certain of the plurality of photosensor cells.Type: GrantFiled: February 25, 2005Date of Patent: March 13, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Chi Fu, Yuan-Hung Liu, Kuo-Yin Lin, Feng-Jia Shiu, Chia-Shiung Tsai, Ching-Sen Kuo, Jieh-Jang Chen
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Patent number: 7101758Abstract: A method for forming triple polysilicon split gate electrodes in a EEPROM flash memory array providing a first gate structure; blanket depositing a first polysilicon layer over the first gate structure; etching back the first polysilicon layer according to a first dry etching process; blanket depositing a second dielectric insulating layer over the first polysilicon layer; blanket depositing a second polysilicon layer over the second dielectric insulating layer; and, lithographically patterning and dry etching according to a respective third and fourth dry etching process through a thickness portion of the respective second and first polysilicon layers to respectively form third and second polysilicon gate electrodes.Type: GrantFiled: October 15, 2003Date of Patent: September 5, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsiang-Fan Lee, Shih-Wei Wang, Yi-Jiun Lin, Kuo-Wei Chu, Ching-Sen Kuo, Chia-Tong Ho
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Publication number: 20060192083Abstract: Described is a light-directing feature formed in the inter-level dielectric (ILD) layer in combination with an anti-reflective (AR) layer to effectively and simultaneously increase quantum efficiency and cross-talk immunity thereby improving photonic performances of photo-sensitive integrated circuits. A plurality of photosensor cells is formed on a semiconductor substrate. An AR layer is subsequently formed on the plurality of photosensor cells, the AR layer being substantially non-reflective of incident light. An ILD layer is then formed over the AR layer, the ILD layer comprising a plurality of light-directing features formed in openings in the ILD layer over the AR layer above and about certain of the plurality of photosensor cells.Type: ApplicationFiled: February 25, 2005Publication date: August 31, 2006Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Chi Fu, Yuan-Hung Liu, Kuo-Yin Lin, Feng-Jia Shiu, Chia-Shiung Tsai, Ching-Sen Kuo, Jieh-Jang Chen
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Publication number: 20050274968Abstract: An image sensor includes a double-microlens structure with an outer microlens aligned over an inner microlens, both microlenses aligned over a corresponding photosensor. The inner or outer microlens may be formed by a silylation process in which a reactive portion of a photoresist material reacts with a silicon-containing agent. The inner or outer microlens may be formed by step etching of a dielectric material, the step etching process including a series of alternating etch steps including an anisotropic etching step and an etching step that causes patterned photoresist to laterally recede. Subsequent isotropic etching processes may be used to smooth the etched step structure and form a smooth lens. A thermally stable and photosensitive polymeric/organic material may also be used to form permanent inner or outer lenses. The photosensitive material is coated then patterned using photolithography, reflowed, then cured to form a permanent lens structure.Type: ApplicationFiled: November 5, 2004Publication date: December 15, 2005Inventors: Ching-Sen Kuo, Feng-Jia Shiu, Gwo-Yuh Shiau, Jieh-Jang Chen, Shih-Chi Fu, Chien Tseng, Chia-Shiung Tsai, Yuan-Hung Liu, Yeur-Luen Tu, Chih-Ta Wu, Chi-Hsin Lo
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Publication number: 20050202631Abstract: A method for forming triple polysilicon split gate electrodes in a EEPROM flash memory array providing a first gate structure; blanket depositing a first polysilicon layer over the first gate structure; etching back the first polysilicon layer according to a first dry etching process; blanket depositing a second dielectric insulating layer over the first polysilicon layer; blanket depositing a second polysilicon layer over the second dielectric insulating layer; and, lithographically patterning and dry etching according to a respective third and fourth dry etching process through a thickness portion of the respective second and first polysilicon layers to respectively form third and second polysilicon gate electrodes.Type: ApplicationFiled: October 15, 2003Publication date: September 15, 2005Inventors: Hsiang-Fan Lee, Shih-Wei Wang, Yi-Jiun Lin, Kuo-Wei Chu, Ching-Sen Kuo, Chia-Tong Ho
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Patent number: 6803291Abstract: A method for protecting an alignment mark area during a CMP process including forming at least a first material layer over a process surface of a semiconductor wafer including active areas and alignment mark trenches formed in the at least one alignment mark area; forming at least a second material layer over the first material layer including the active areas and the at least one alignment mark area; lithographically patterning and etching the at least a second material layer to form at least a plurality lines of the at least a second material layer adjacent to the alignment mark trenches; and, carrying out a CMP process to remove at least a portion of the at least a second material layer.Type: GrantFiled: March 20, 2003Date of Patent: October 12, 2004Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Shih-Chi Fu, Feng-Jia Shih, Chia-Tung Ho, Chih-Ta Wu, Ching-Sen Kuo, Jieh-Jang Chen, Gwo-Yuh Shiau, Chia-Shiung Tsia
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Publication number: 20040185637Abstract: A method for protecting an alignment mark area during a CMP process including forming at least a first material layer over a process surface of a semiconductor wafer including active areas and alignment mark trenches formed in the at least one alignment mark area; forming at least a second material layer over the first material layer including the active areas and the at least one alignment mark area; lithographically patterning and etching the at least a second material layer to form at least a plurality lines of the at least a second material layer adjacent to the alignment mark trenches; and, carrying out a CMP process to remove at least a portion of the at least a second material layer.Type: ApplicationFiled: March 20, 2003Publication date: September 23, 2004Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.,Inventors: Shih-Chi Fu, Feng-Jia Shiu, Chia-Tung Ho, Chih-Ta Wu, Ching-Sen Kuo, Jieh-Jang Chen, Gwo-Yuh Shiau, Chia-Shiung Tsia
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Patent number: 6645851Abstract: A method of forming a planarized photoresist coating on a substrate having holes with different duty ratios is described. A first photoresist preferably comprised of a Novolac resin and a diazonaphthoquinone photoactive compound is coated on a substrate and baked at or slightly above its Tg so that it reflows and fills the holes. The photoresist is exposed without a mask at a dose that allows the developer to thin the photoresist to a recessed depth within the holes. After the photoresist is hardened with a 250° C. bake, a second photoresist is coated on the substrate to form a planarized film with a thickness variation of less than 50 Angstroms between low and high duty ratio hole regions. One application is where the second photoresist is used to form a trench pattern in a via first dual damascene method. Secondly, the method is useful in fabricating MIM capacitors.Type: GrantFiled: September 17, 2002Date of Patent: November 11, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chia-Tung Ho, Feng-Jia Shih, Jieh-Jang Chen, Ching-Sen Kuo, Shih-Chi Fu, Gwo-Yuh Shiau, Chia-Shiung Tsia
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Patent number: 6632590Abstract: A new method is provided for the creation of densely patterned interconnect lines. As a first step of the invention, the mask layout is modified such that the ratio of line width (L) to line spacing (S) is sharply decreased. The line pattern that is created using this mask reflects the same sharp reduction in the ratio L/S. The width of the thus created lines is, as a second step of the invention, increased by the process of thermal flow while the spacing between the lines is concurrently decreased by the same amount.Type: GrantFiled: July 14, 2000Date of Patent: October 14, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: San-De Tzu, Tsung-Hou Lee, Chih-Hsiung Lee, Gwo Yuh Shiau, Ching-sen Kuo
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Patent number: RE41697Abstract: A method of forming a planarized photoresist coating on a substrate having holes with different duty ratios is described. A first photoresist preferably comprised of a Novolac resin and a diazonaphthoquinone photoactive compound is coated on a substrate and baked at or slightly above its Tg so that it reflows and fills the holes. The photoresist is exposed without a mask at a dose that allows the developer to thin the photoresist to a recessed depth within the holes. After the photoresist is hardened with a 250° C. bake, a second photoresist is coated on the substrate to form a planarized film with a thickness variation of less than 50 Angstroms between low and high duty ratio hole regions. One application is where the second photoresist is used to form a trench pattern in a via first dual damascene method. Secondly, the method is useful in fabricating MIM capacitors.Type: GrantFiled: September 26, 2005Date of Patent: September 14, 2010Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chia-Tung Ho, Feng-Jia Shih, Jieh-Jang Chen, Ching-Sen Kuo, Shih-Chi Fu, Gwo-Yuh Shiau, Chia-Shiung Tsai