Patents by Inventor Ching-Sen Kuo
Ching-Sen Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10734436Abstract: A first photoresist pattern and a second photoresist pattern are formed over a substrate. The first photoresist pattern is separated from the second photoresist pattern by a gap. A chemical mixture is coated on the first and second photoresist patterns. The chemical mixture contains a chemical material and surfactant particles mixed into the chemical material. The chemical mixture fills the gap. A baking process is performed on the first and second photoresist patterns, the baking process causing the gap to shrink. At least some surfactant particles are disposed at sidewall boundaries of the gap. A developing process is performed on the first and second photoresist patterns. The developing process removes the chemical mixture in the gap and over the photoresist patterns. The surfactant particles disposed at sidewall boundaries of the gap reduce a capillary effect during the developing process.Type: GrantFiled: September 26, 2018Date of Patent: August 4, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Chao Chiu, Chih-Chien Wang, Feng-Jia Shiu, Ching-Sen Kuo, Chun-Wei Chang, Kai Tzeng
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Publication number: 20200135538Abstract: In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.Type: ApplicationFiled: September 26, 2019Publication date: April 30, 2020Inventors: Tsai-Ming HUANG, Wei-Chieh HUANG, Hsun-Chung KUANG, Yen-Chang CHU, Cheng-Che CHUNG, Chin-Wei LIANG, Ching-Sen KUO, Jieh-Jang CHEN, Feng-Jia SHIU, Sheng-Chau CHEN
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Publication number: 20200127000Abstract: A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer.Type: ApplicationFiled: December 19, 2019Publication date: April 23, 2020Inventors: Chun-Chang Wu, Chihy-Yuan Cheng, Sz-Fan Chen, Shun-Shing Yang, Wei-Lin Chang, Ching-Sen Kuo, Feng-Jia Shiu, Chun-Chang Chen
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Publication number: 20200075318Abstract: In a method of manufacturing a semiconductor device, a first layer having an opening is formed over a substrate. A second layer is formed over the first layer and the substrate. A photo resist pattern is formed over the second layer above the opening of the first layer. The photo resist pattern is reflowed by a thermal process. An etch-back operation is performed to planarize the second layer.Type: ApplicationFiled: May 30, 2019Publication date: March 5, 2020Inventors: Cheng-Che CHUNG, Yi Jen TSAI, Ching-Sen KUO, Tsai-Ming HUANG, Jieh-Jang CHEN, Feng-Jia SHIU
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Publication number: 20200058545Abstract: A method for manufacturing a semiconductor device includes forming a structure protruding from a substrate, forming a dielectric layer covering the structure, forming a dummy layer covering the dielectric layer, and performing a planarization process to completely remove the dummy layer. A material of the dummy layer has a slower removal rate to the planarization process than a material of the dielectric layer.Type: ApplicationFiled: October 25, 2019Publication date: February 20, 2020Inventors: Wei-Chieh HUANG, Chin-Wei LIANG, Feng-Jia SHIU, Hsia-Wei CHEN, Jieh-Jang CHEN, Ching-Sen KUO
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Patent number: 10546889Abstract: Implementations of the disclosure provide a method of fabricating an image sensor device. The method includes forming first trenches in a first photoresist layer using a first photomask having a first pattern to expose a first surface of a substrate, directing ions into the exposed first substrate through the first trenches to form first isolation regions in the substrate, removing the first photoresist layer, forming second trenches in a second photoresist layer using a second photomask having a second pattern to expose a second surface of the substrate, the second pattern being shifted diagonally from the first pattern by half mask pitch, directing ions into the exposed second surface through the second trenches to form second isolation regions in the substrate, the first and second isolation regions being alternatingly disposed in the substrate, and the first and second isolation regions defining pixel regions therebetween, and removing the second photoresist layer.Type: GrantFiled: November 5, 2018Date of Patent: January 28, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Chao Chiu, Chih-Chien Wang, Feng-Jia Shiu, Ching-Sen Kuo, Chun-Wei Chang, Kai Tzeng
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Patent number: 10522557Abstract: A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer.Type: GrantFiled: October 30, 2017Date of Patent: December 31, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Chang Wu, Chihy-Yuan Cheng, Sz-Fan Chen, Shun-Shing Yang, Wei-Lin Chang, Ching-Sen Kuo, Feng-Jia Shiu, Chun-Chang Chen
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Patent number: 10510587Abstract: A method for manufacturing a semiconductor device includes forming a structure protruding from a substrate, forming a dielectric layer covering the structure, forming a dummy layer covering the dielectric layer, and performing a planarization process to completely remove the dummy layer. A material of the dummy layer has a slower removal rate to the planarization process than a material of the dielectric layer.Type: GrantFiled: February 26, 2018Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Chieh Huang, Chin-Wei Liang, Feng-Jia Shiu, Hsia-Wei Chen, Jieh-Jang Chen, Ching-Sen Kuo
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Patent number: 10366916Abstract: A semiconductor structure includes a substrate having a first region and a second region being adjacent each other; a first patterned layer formed on the substrate, wherein the first patterned layer includes first features in the first region, wherein the second region is free of the patterned layer; and a first guard ring disposed in the second region and surrounding the first features, wherein the first guard ring includes a first width W1 and is spaced a first distance D1 from the first features, W1 being greater than D1.Type: GrantFiled: March 12, 2018Date of Patent: July 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chihy-Yuan Cheng, Chun-Chang Wu, Shun-Shing Yang, Ching-Sen Kuo, Feng-Jia Shiu, Chun-Chang Chen
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Publication number: 20190131313Abstract: A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer.Type: ApplicationFiled: October 30, 2017Publication date: May 2, 2019Inventors: Chun-Chang Wu, Chihy-Yuan Cheng, Sz-Fan Chen, Shun-Shing Yang, Wei-Lin Chang, Ching-Sen Kuo, Feng-Jia Shiu, Chun-Chang Chen
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Publication number: 20190103307Abstract: A method for manufacturing a semiconductor device includes forming a structure protruding from a substrate, forming a dielectric layer covering the structure, forming a dummy layer covering the dielectric layer, and performing a planarization process to completely remove the dummy layer. A material of the dummy layer has a slower removal rate to the planarization process than a material of the dielectric layer.Type: ApplicationFiled: February 26, 2018Publication date: April 4, 2019Inventors: Wei-Chieh HUANG, Chin-Wei LIANG, Feng-Jia SHIU, Hsia-Wei CHEN, Jieh-Jang CHEN, Ching-Sen KUO
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Publication number: 20190088694Abstract: Implementations of the disclosure provide a method of fabricating an image sensor device. The method includes forming first trenches in a first photoresist layer using a first photomask having a first pattern to expose a first surface of a substrate, directing ions into the exposed first substrate through the first trenches to form first isolation regions in the substrate, removing the first photoresist layer, forming second trenches in a second photoresist layer using a second photomask having a second pattern to expose a second surface of the substrate, the second pattern being shifted diagonally from the first pattern by half mask pitch, directing ions into the exposed second surface through the second trenches to form second isolation regions in the substrate, the first and second isolation regions being alternatingly disposed in the substrate, and the first and second isolation regions defining pixel regions therebetween, and removing the second photoresist layer.Type: ApplicationFiled: November 5, 2018Publication date: March 21, 2019Inventors: Wei-Chao CHIU, Chih-Chien WANG, Feng-Jia SHIU, Ching-Sen KUO, Chun-Wei CHANG, Kai TZENG
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Publication number: 20190027530Abstract: A first photoresist pattern and a second photoresist pattern are formed over a substrate. The first photoresist pattern is separated from the second photoresist pattern by a gap. A chemical mixture is coated on the first and second photoresist patterns. The chemical mixture contains a chemical material and surfactant particles mixed into the chemical material. The chemical mixture fills the gap. A baking process is performed on the first and second photoresist patterns, the baking process causing the gap to shrink. At least some surfactant particles are disposed at sidewall boundaries of the gap. A developing process is performed on the first and second photoresist patterns. The developing process removes the chemical mixture in the gap and over the photoresist patterns. The surfactant particles disposed at sidewall boundaries of the gap reduce a capillary effect during the developing process.Type: ApplicationFiled: September 26, 2018Publication date: January 24, 2019Inventors: Wei-Chao Chiu, Chih-Chien Wang, Feng-Jia Shiu, Ching-Sen Kuo, Chun-Wei Chang, Kai Tzeng
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Publication number: 20190027519Abstract: Various examples of a technique for forming a pattern for substrate fabrication are disclosed herein. In an example, a method includes receiving a substrate. A patterned resist is formed on the substrate and has a trench defined therein. A dielectric is deposited on the patterned resist and within the trench such that the dielectric narrows a width of the trench to further define the trench. A fabrication process is performed on a region of the substrate underlying the trench defined by the dielectric.Type: ApplicationFiled: July 18, 2017Publication date: January 24, 2019Inventors: Wei-Chao Chiu, Kai Tzeng, Chih-Chien Wang, Chun-Wei Chang, Ching-Sen Kuo, Feng-Jia Shiu, Cheng-Ta Wu
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Patent number: 10186542Abstract: Various examples of a technique for forming a pattern for substrate fabrication are disclosed herein. In an example, a method includes receiving a substrate. A patterned resist is formed on the substrate and has a trench defined therein. A dielectric is deposited on the patterned resist and within the trench such that the dielectric narrows a width of the trench to further define the trench. A fabrication process is performed on a region of the substrate underlying the trench defined by the dielectric.Type: GrantFiled: July 18, 2017Date of Patent: January 22, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Chao Chiu, Kai Tzeng, Chih-Chien Wang, Chun-Wei Chang, Ching-Sen Kuo, Feng-Jia Shiu, Cheng-Ta Wu
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Patent number: 10121811Abstract: Implementations of the disclosure provide a method of fabricating an image sensor device. The method includes forming first trenches in a first photoresist layer using a first photomask having a first pattern to expose a first surface of a substrate, directing ions into the exposed first substrate through the first trenches to form first isolation regions in the substrate, removing the first photoresist layer, forming second trenches in a second photoresist layer using a second photomask having a second pattern to expose a second surface of the substrate, the second pattern being shifted diagonally from the first pattern by half mask pitch, directing ions into the exposed second surface through the second trenches to form second isolation regions in the substrate, the first and second isolation regions being alternatingly disposed in the substrate, and the first and second isolation regions defining pixel regions therebetween, and removing the second photoresist layer.Type: GrantFiled: August 25, 2017Date of Patent: November 6, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Chao Chiu, Chih-Chien Wang, Feng-Jia Shiu, Ching-Sen Kuo, Chun-Wei Chang, Kai Tzeng
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Patent number: 10090357Abstract: A first photoresist pattern and a second photoresist pattern are formed over a substrate. The first photoresist pattern is separated from the second photoresist pattern by a gap. A chemical mixture is coated on the first and second photoresist patterns. The chemical mixture contains a chemical material and surfactant particles mixed into the chemical material. The chemical mixture fills the gap. A baking process is performed on the first and second photoresist patterns, the baking process causing the gap to shrink. At least some surfactant particles are disposed at sidewall boundaries of the gap. A developing process is performed on the first and second photoresist patterns. The developing process removes the chemical mixture in the gap and over the photoresist patterns. The surfactant particles disposed at sidewall boundaries of the gap reduce a capillary effect during the developing process.Type: GrantFiled: March 7, 2016Date of Patent: October 2, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Chao Chiu, Chih-Chien Wang, Feng-Jia Shiu, Ching-Sen Kuo, Chun-Wei Chang, Kai Tzeng
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Publication number: 20180204758Abstract: A semiconductor structure includes a substrate having a first region and a second region being adjacent each other; a first patterned layer formed on the substrate, wherein the first patterned layer includes first features in the first region, wherein the second region is free of the patterned layer; and a first guard ring disposed in the second region and surrounding the first features, wherein the first guard ring includes a first width W1 and is spaced a first distance D1 from the first features, W1 being greater than D1.Type: ApplicationFiled: March 12, 2018Publication date: July 19, 2018Inventors: Chihy-Yuan Cheng, Chun-Chang Wu, Shun-Shing Yang, Ching-Sen Kuo, Feng-Jia Shiu, Chun-Chang Chen
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Publication number: 20180076081Abstract: A method includes forming a patterned layer on a substrate having a first region and a second region being adjacent each other. The patterned layer includes first features in the first region. The second region is free of the patterned layer. The method further includes forming a material layer on the patterned layer and the substrate; forming a first guard ring disposed in the second region and surrounding the first features; forming a flowable-material (FM) layer over the material layer; forming a patterned resist layer over the FM layer, wherein the patterned resist layer includes a plurality of openings; and transferring the plurality of openings to the material layer.Type: ApplicationFiled: September 9, 2016Publication date: March 15, 2018Inventors: Chihy-Yuan Cheng, Chun-Chang Wu, Shun-Shing Yang, Ching-Sen Kuo, Feng-Jia Shiu, Chun-Chang Chen
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Patent number: 9917006Abstract: A method includes forming a patterned layer on a substrate having a first region and a second region being adjacent each other. The patterned layer includes first features in the first region. The second region is free of the patterned layer. The method further includes forming a material layer on the patterned layer and the substrate; forming a first guard ring disposed in the second region and surrounding the first features; forming a flowable-material (FM) layer over the material layer; forming a patterned resist layer over the FM layer, wherein the patterned resist layer includes a plurality of openings; and transferring the plurality of openings to the material layer.Type: GrantFiled: September 9, 2016Date of Patent: March 13, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chihy-Yuan Cheng, Chun-Chang Wu, Shun-Shing Yang, Ching-Sen Kuo, Feng-Jia Shiu, Chun-Chang Chen