Abstract: An erasable programmable read only memory includes two serially connected P-type metal-oxide semiconductor (MOS) transistors, wherein a first P-type MOS transistor acts as select transistor, a gate of the first P-type MOS transistor is coupled to select gate voltage, a first node of the first P-type MOS transistor connected to source line voltage, a second node of the first P-type MOS transistor connected to a first node of a second P-type MOS transistor, wherein a second node of the second P-type MOS transistor is connected to bit line voltage, wherein a gate of the second P-type MOS transistor serves as a floating gate, wherein the erasable programmable read only memory does not need to bias a certain voltage on a control gate for programming and thereby injecting hot carriers onto the floating gate, and wherein the erasable programmable read only memory is capped by dielectric materials which are transparent to ultraviolet (UV) light.

Abstract: A method for writing a memory module includes providing a plurality of memory cells, applying a first transmission line voltage to the first transmission line of the column of a memory cell, turning on a P-type channel of a memory cell between the memory cell to be written and the first transmission line of the column of the memory cell, turning off the P-type channel of at least one memory cell between the memory cell and the second transmission line of the column of the memory cell, applying a word line voltage to a word line connected to the memory cell, in order to inject hot electrons on a junction between the substrate and the first P-type doped region of the memory cell into a silicon nitride layer of the memory cell using band-to-band tunneling injection, and applying a substrate voltage to the substrates of the plurality of memory cells.

Abstract: A low-voltage nonvolatile memory array includes a cell well of a first conductivity type formed in a substrate; columns of buried bit lines of a second conductivity type formed within the cell well, wherein columns of the buried bit lines are isolated from each other and each is further divided into of sub-bit line segments with deeply doped source wells of the first conductivity type connected to the cell well; a plurality of memory cell blocks serially arranged over one of the columns of buried bit lines, wherein a memory cell block corresponds to a sub-bit line segment, and each memory cell block includes at least one memory transistor having a stacked gate, source, and drain; and a local bit line overlying the memory cell blocks and electrically connected to the drain of the memory transistor via a contact plug short-circuiting the drain and the subjacent buried bit line.

Abstract: A method of programming and erasing a non-volatile semiconductor memory is provided. The memory device for such operation has one first conductivity substrate (10), a plurality of second conductivity deep ion wells (12), a plurality of shallow ion wells (14), a plurality of memory cell arrays disposed above the shallow ion wells (14), a plurality of bit lines (BL) connected to the shallow ion wells (14) through respective conductive plugs (18), and a plurality of shallow trench insulation (STI) layers (16) above the substrate (10). The programming of memory cells with multi-level data storage takes a threshold voltage (Vth) in the negative voltage range, whilst the erasing of memory cells takes a threshold voltage (Vth) in the positive voltage range. The erasing operation is performed in conjunction with a self-limiting means to prevent continuous ascending of the threshold voltage (Vth) as the erasing operation is in progress.

Abstract: A method of programming and erasing a non-volatile semiconductor memory is provided. The memory device for such operation has one first conductivity substrate (10), a plurality of second conductivity deep ion wells (12), a plurality of shallow ion wells (14), a plurality of memory cell arrays disposed above the shallow ion wells (14), a plurality of bit lines (BL) connected to the shallow ion wells (14) through respective conductive plugs (18), and a plurality of shallow trench insulation (STI) layers (16) above the substrate (10). The programming of memory cells with multi-level data storage takes a threshold voltage (Vth) in the negative voltage range, whilst the erasing of memory cells takes a threshold voltage (Vth) in the positive voltage range. The erasing operation is performed in conjunction with a self-limiting means to prevent continuous ascending of the threshold voltage (Vth) as the erasing operation is in progress.

Abstract: A low-voltage nonvolatile memory array includes a cell well of a first conductivity type formed in a substrate; columns of buried bit lines of a second conductivity type formed within the cell well, wherein columns of the buried bit lines are isolated from each other and each is further divided into of sub-bit line segments with deeply doped source wells of the first conductivity type connected to the cell well; a plurality of memory cell blocks serially arranged over one of the columns of buried bit lines, wherein a memory cell block corresponds to a sub-bit line segment, and each memory cell block includes at least one memory transistor having a stacked gate, source, and drain; and a local bit line overlying the memory cell blocks and electrically connected to the drain of the memory transistor via a contact plug short-circuiting the drain and the subjacent buried bit line.

Abstract: A low voltage single-poly flash memory cell includes a first ion well of a first conductivity type, a second ion well of a second conductivity type formed on the first ion well, a charge storage layer comprising a first insulating layer, a trapping layer, and a second insulating layer, located on the second ion well, a gate located on the charge storage layer, a sourceand a drain of the second conductivity type located in two sides of the charge storage layer, and an ion doped region of the first conductivity type formed in the second ion well and under and surrounding the source and at least a portion of a bottom of the first insulating layer.

Abstract: An erasable programmable read only memory includestwo serially connected P-type metal-oxide semiconductor (MOS) transistors,wherein a first P-type MOS transistor acts as selecttransistor, a gate of the first P-type MOS transistor is coupled to select gate voltage, a first node of the firstP-type MOS transistor connected to source linevoltage, a second node of the first P-type MOS transistor connected to a first node of a second P-type MOS transistor, wherein a second node of the second P-type MOS transistor is connected to bit line voltage, wherein a gate of the secondP-type MOS transistor serves as a floating gate, wherein the erasable programmable read only memory does not need to bias a certain voltage on a control gate for programming and thereby injecting hot carriers onto the floating gate, and wherein the erasable programmable read only memory is capped by dielectric materials which are transparent to ultraviolet (UV) light.

Abstract: A novel structure of nonvolatile memory is disclosed. The nonvolatile memory includes two serially connected PMOS transistors. The characteristic of the devices is that bias is not necessary to apply to the floating gate during the programming mode. Thus, the control gate is omitted for the structure or layout, thereby saving the space for making the control gate. The carrier may be “automatically injected” into floating gate for programming the status of the devices.

Abstract: A flash memory array and related method for programming, erasing, and reading. The memory includes: a plurality of memory cells, each memory cell having a gate, a drain, a source, and a body; a plurality of word lines and body lines. The bodies of the memory cells whose gates are connected to a same word line are connected to a same body line, and the body lines are isolated from each other such that different body lines can be driven to have different voltages. When the memory programs, erases, and reads data, the different body lines are driven to different voltage.

Abstract: A low-voltage nonvolatile memory array includes an N type semiconductor substrate having a memory region. A deep P well is formed in the semiconductor substrate. A cell N well is located within the memory region in the semiconductor substrate. The cell N well is situated above the deep ion well. A shallow P well serving as a buried bit line is doped within the cell ion well. The shallow P well is isolated by an STI layer, wherein the STI layer has a thickness greater than a well depth of the shallow ion well. At least one memory transistor with a stacked gate, a source, and a drain is formed on the shallow ion well. The source of the memory transistor is electrically coupled to the cell N well to induce a capacitor between the cell N well and the deep P well during a read operation, thereby avoiding read current bounce or potential power crash.

Abstract: The present invention relates to a structure of an embedded channel write/erase flash memory cell and a fabricating method thereof and, more particularly, to a structure combining CMOS devices and flash memory cells, wherein flash memory cell structures and CMOS devices are simultaneously fabricated on a substrate to reduce the cost and to simplify the process flow. Moreover, CMOS devices capable of performing high-voltage and low-voltage operations are reserved. Therefore, the present invention can not only effectively improve the operating efficiency of flash memory cells and CMOS devices, but its whole volume is also smaller than that obtained by combining separately designed and fabricated CMOS devices and flash memory cells.

Abstract: A flash memory structure and method of fabrication is introduced. The flash memory structure includes a plurality of parallel word lines positioned on a semiconductor substrate, a plurality of parallel source lines with first conductivity type positioned perpendicularly to the word lines and within the semiconductor substrate, two bit lines with first conductivity type positioned on two sides of each source line and within the semiconductor substrate, a doped region with second conductivity type positioned beneath and surrounding each bit line, a contact plug positioned in each bit line for electrically connecting to the bit line and a corresponding doped region beneath and surrounding the bit line, and a gate positioned on an overlapped region of the semiconductor substrate and each word line.

Abstract: A single-poly EEPROM is disxlosed. The single-poly EEPROM includes a first PMOS transistor that is serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P-type substrate. The first PMOS transistor includes a floating gate, a first P+ doped drain region, and a first P+ doped source region. The second PMOS transistor includes a gate and second P+ doped source region. The first P+ doped source region of the first PMOS trasistor serves as a drain of the second PMOS transistor. An erase gate extending to the floating gate for erasing the single-poly EEPROM is provided in the P-type substrate.

Abstract: A non-volatile semiconuctor memory device having divided bit lines. A main bit line controlled by at least one bit line selection device to transfer its potential selected sub bit line, such that memory cells in a selected work and overloading of the bit line generated by a parasitic capacitance can be prevented. The memory cells and the bit line selection device arranged in parallel in a P-well and a N-well, respectively, thereby preventing disturbances during programming or erasing the bit line.

Abstract: The present invention relates to a structure of a low-voltage channel write/erase flash memory cell and a fabricating method thereof, which structure comprises an N-substrate, a deep P-well formed on the substrate, and an N-well formed on the deep P-well. A deep p-type region and a shallow p-type region are ion-implanted in the N-well. The deep p-type region is connected to the shallow p-type region. An n-type region is ion-implanted in the deep p-type region to be electrically shorted with the deep p-type region and be used as a drain. Another n-type region is also ion-implanted at one side of the shallow p-type region to be used as a source.

Abstract: An erasable programmable read only memory comprising two serially connected P-type metal-oxide semiconductor (MOS) transistors wherein the control gate is omitted in the structure for layout as the bias is not necessary to apply to the floating gate during the programming mode.

Abstract: A single-poly EEPROM is disclosed. The single-poly EEPROM includes a first PMOS transistor that is serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P-type substrate. The first PMOS transistor includes a floating gate, a first P+ doped drain region, and a first P+ doped source region. The second PMOS transistor includes a gate and second P+ doped source region. The first P+ doped drain region of the first PMOS transistor serves as a drain of the second PMOS transistor. An erase gate extending to the floating gate for erasing the single-poly EEPROM is provided in the P-type substrate.

Abstract: A pseudo-dynamic operating method and a flash memory cell capable of performing this operating method are disclosed. A parasitic capacitor near the drain terminal of the flash memory can be charged in few microseconds during operation. Interference generated between the floating gate and the source is avoided by using a first oxide layer which is thicker at the interface between floating gate and source and thinner near central part under stacked gate.

Abstract: A low voltage single-poly flash memory cell includes a first ion well of a first conductivity type, a second ion well of a second conductivity type formed on the first ion well, a charge storage layer comprising a first insulating layer, a trapping layer, and a second insulating layer, located on the second ion well, a gate located on the charge storage layer, a sourceand a drain of the second conductivity type located in two sides of the charge storage layer, and an ion doped region of the first conductivity type formed in the second ion well and under and surrounding the source and at least a portion of a bottom of the first insulating layer.