Patents by Inventor Ching-Sung Yang
Ching-Sung Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080316791Abstract: The present invention provides a method of operating a one-time programmable read only memory (OTPROM). The OTPROM includes at least a select transistor, an electrode and a dielectric layer disposed on a substrate, wherein the electrode is set up on the source region of the select transistor and the dielectric layer is set up between the electrode and the source region. The method of operating the one-time programmable read only memory includes performing a programming operation to write a digital data value of ‘1’ into the memory and performing a programming operation to write a digital data value of ‘0’ into the memory.Type: ApplicationFiled: August 14, 2008Publication date: December 25, 2008Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Ching-Sung Yang, Wei-Zhe Wong, Chih-Chen Cho
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Patent number: 7462902Abstract: A nonvolatile memory is provided. The memory includes a select transistor and a trench transistor. The select transistor is formed on the substrate. The select transistor includes a first gate formed on the substrate and first and second source/drain regions formed in the substrate next to the first gate. The trench transistor is formed in the substrate. The trench transistor includes a second gate formed in the trench of substrate, an electron trapping layer formed between the second gate and the trench and second and third source/drain regions formed in the substrate next to the second gate. The select transistor and the trench transistor share the second source/drain region.Type: GrantFiled: June 13, 2005Date of Patent: December 9, 2008Assignee: Powerchip Semiconductor Corp.Inventors: Ching-Sung Yang, Wei-Zhe Wong, Chih-Chen Cho
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Patent number: 7452775Abstract: A non-volatile memory device having a substrate, an n type well, a p type well, a control gate, a composite dielectric layer, a source region and a drain region is provided. A trench is formed in the substrate. The n type well is formed in the substrate. The p type well is formed in the substrate above the n type well. The junction of p type well and the n type well is higher than the bottom of the trench. The control gate which protruding the surface of substrate is formed on the sidewalls of the trench. The composite dielectric layer is formed between the control gate and the substrate. The composite dielectric layer includes a charge-trapping layer. The source region and the drain region are formed in the substrate of the bottom of the trench respectively next to the sides of the control gate.Type: GrantFiled: November 10, 2006Date of Patent: November 18, 2008Assignee: Powership Semiconductor Corp.Inventors: Wei-Zhe Wong, Ching-Sung Yang, Chih-Chen Cho
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Patent number: 7436028Abstract: A one-time programmable read only memory is provided. The memory includes a substrate, a select transistor, an electrode and a dielectric layer. The select transistor is formed on the substrate. The electrode is formed over the source region of the select transistor. The dielectric layer is formed between the electrode and the source region of the select transistor. Digital data is stored in the memory through the breakdown or not of the dielectric layer.Type: GrantFiled: June 2, 2005Date of Patent: October 14, 2008Assignee: Powerchip Semiconductor Corp.Inventors: Ching-Sung Yang, Wei-Zhe Wong, Chih-Chen Cho
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Publication number: 20080227282Abstract: A non-volatile memory is provided. A substrate having a number of trenches and a number of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjacent trenches respectively. A number of select gate dielectric layers are disposed between the select gates and the substrate. A number of composite layers are disposed over the surface of the trenches and each composite layer has a charge trapping layer. A number of word lines are arranged in parallel in a second direction, wherein each of the word lines fills the trenches between adjacent select gates and is disposed over the composite layers.Type: ApplicationFiled: April 23, 2008Publication date: September 18, 2008Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Wei-Zhe Wong, Ching-Sung Yang
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Publication number: 20080198669Abstract: A non-volatile memory is provided. A substrate having a number of trenches and a number of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjacent trenches respectively. A number of select gate dielectric layers are disposed between the select gates and the substrate. A number of composite layers are disposed over the surface of the trenches and each composite layer has a charge trapping layer. A number of word lines are arranged in parallel in a second direction, wherein each of the word lines fills the trenches between adjacent select gates and is disposed over the composite layers.Type: ApplicationFiled: April 23, 2008Publication date: August 21, 2008Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Wei-Zhe Wong, Ching-Sung Yang
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Patent number: 7397080Abstract: A non-volatile memory including at least a substrate, a memory cell and source/drain regions is provided. The memory cell is disposed on the substrate and includes at least a first memory unit and a second memory unit. Wherein, the first memory unit, from the substrate up, includes a floating gate and a first control gate. The second memory unit is disposed on a sidewall of the first memory unit and includes a charge trapping layer and a second control gate. The two source/drain regions are disposed in the substrate at both sides of the memory cell.Type: GrantFiled: December 15, 2005Date of Patent: July 8, 2008Assignee: Powerchip Semiconductor Corp.Inventors: Wei-Zhe Wong, Ching-Sung Yang
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Publication number: 20080151645Abstract: A non-volatile memory including at least a substrate, a memory cell and source/drain regions is provided. The memory cell is disposed on the substrate and includes at least a first memory unit and a second memory unit. Wherein, the first memory unit, from the substrate up, includes a floating gate and a first control gate. The second memory unit is disposed on a sidewall of the first memory unit and includes a charge trapping layer and a second control gate. The two source/drain regions are disposed in the substrate at both sides of the memory cell.Type: ApplicationFiled: March 6, 2008Publication date: June 26, 2008Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Wei-Zhe Wong, Ching-Sung Yang
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Publication number: 20080153232Abstract: A non-volatile memory including at least a substrate, a memory cell and source/drain regions is provided. The memory cell is disposed on the substrate and includes at least a first memory unit and a second memory unit. Wherein, the first memory unit, from the substrate up, includes a floating gate and a first control gate. The second memory unit is disposed on a sidewall of the first memory unit and includes a charge trapping layer and a second control gate. The two source/drain regions are disposed in the substrate at both sides of the memory cell.Type: ApplicationFiled: March 6, 2008Publication date: June 26, 2008Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Wei-Zhe Wong, Ching-Sung Yang
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Patent number: 7391078Abstract: A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjacent trenches respectively. A plurality of select gate dielectric layers are disposed between the select gates and the substrate. A plurality of composite layers are disposed over the surface of the trenches and each composite layer has a charge trapping layer. A plurality of word lines are arranged in parallel in a second direction, wherein each of the word lines fills the trenches between adjacent select gates and is disposed over the composite layers.Type: GrantFiled: August 2, 2005Date of Patent: June 24, 2008Assignee: Powerchip Semiconductor Corp.Inventors: Wei-Zhe Wong, Ching-Sung Yang
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Patent number: 7335559Abstract: A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are located in the substrate at the peripheries of the stacked gate structures; each of the pocket doped regions extends under the stacked gate structure. Drain regions are located in the pocket doped regions at the peripheries of the stacked gate structures. An auxiliary gate layer is located on the substrate between the stacked gate structures. A gate dielectric layer is located between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stacked gate structure. Plugs are located on the substrate and extended to connect with the pocket doped region and the drain regions therein.Type: GrantFiled: July 17, 2007Date of Patent: February 26, 2008Assignee: Powerchip Semiconductor Corp.Inventors: Wei-Zhe Wong, Ching-Sung Yang, Chih-Chen Cho
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Patent number: 7336539Abstract: A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked gate structure. A select gate is disposed between the stacked gate structure and the source region. A first gate dielectric layer is disposed between the select gate and the stacked gate structure. A second gate dielectric layer is disposed between the select gate and the substrate. A shallow doped region is disposed in the substrate under the stacked gate structure and the select gate. A deep doped region is disposed in the substrate on one side of the stacked gate structure. The conductive plug on the substrate extends through the drain region and the deep doped region.Type: GrantFiled: May 17, 2007Date of Patent: February 26, 2008Assignee: Powerchip Semiconductor Corp.Inventors: Wei-Zhe Wong, Ching-Sung Yang
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Publication number: 20070263448Abstract: A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are located in the substrate at the peripheries of the stacked gate structures; each of the pocket doped regions extends under the stacked gate structure. Drain regions are located in the pocket doped regions at the peripheries of the stacked gate structures. An auxiliary gate layer is located on the substrate between the stacked gate structures. A gate dielectric layer is located between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stacked gate structure. Plugs are located on the substrate and extended to connect with the pocket doped region and the drain regions therein.Type: ApplicationFiled: July 17, 2007Publication date: November 15, 2007Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Wei-Zhe Wong, Ching-Sung Yang, Chih-Chen Cho
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Publication number: 20070259497Abstract: A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are located in the substrate at the peripheries of the stacked gate structures; each of the pocket doped regions extends under the stacked gate structure. Drain regions are located in the pocket doped regions at the peripheries of the stacked gate structures. An auxiliary gate layer is located on the substrate between the stacked gate structures. A gate dielectric layer is located between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stacked gate structure. Plugs are located on the substrate and extended to connect with the pocket doped region and the drain regions therein.Type: ApplicationFiled: July 17, 2007Publication date: November 8, 2007Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Wei-Zhe Wong, Ching-Sung Yang, Chih-Chen Cho
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Patent number: 7291882Abstract: A programmable and erasable digital switch device is provided. An N-type memory transistor and a P-type memory transistor are formed over a substrate. The N-type memory transistor includes a first N-type doped region, a second N-type doped region, a first charge storage layer and a first control gate. The P-type memory transistor includes a first P-type doped region, a second P-type doped region, a second charge storage layer and a second control gate. A common bit line doped region is formed between the N-type memory transistor and the P type memory transistor and electrically connects the first N-type region to the second P-type doped region. A word line electrically connects the first control gate to the second control gate.Type: GrantFiled: September 27, 2005Date of Patent: November 6, 2007Assignee: Powerchip Semiconductor Corp.Inventors: Ching-Sung Yang, Wei-Zhe Wong
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Patent number: 7274062Abstract: A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are located in the substrate at the peripheries of the stacked gate structures; each of the pocket doped regions extends under the stacked gate structure. Drain regions are located in the pocket doped regions at the peripheries of the stacked gate structures. An auxiliary gate layer is located on the substrate between the stacked gate structures. A gate dielectric layer is located between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stacked gate structure. Plugs are located on the substrate and extended to connect with the pocket doped region and the drain regions therein.Type: GrantFiled: August 29, 2005Date of Patent: September 25, 2007Assignee: Powerchip Semiconductor Corp.Inventors: Wei-Zhe Wong, Ching-Sung Yang, Chih-Chen Cho
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Publication number: 20070217267Abstract: A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked gate structure. A select gate is disposed between the stacked gate structure and the source region. A first gate dielectric layer is disposed between the select gate and the stacked gate structure. A second gate dielectric layer is disposed between the select gate and the substrate. A shallow doped region is disposed in the substrate under the stacked gate structure and the select gate. A deep doped region is disposed in the substrate on one side of the stacked gate structure. The conductive plug on the substrate extends through the drain region and the deep doped region.Type: ApplicationFiled: May 17, 2007Publication date: September 20, 2007Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Wei-Zhe Wong, Ching-Sung Yang
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Publication number: 20070218634Abstract: A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked gate structure. A select gate is disposed between the stacked gate structure and the source region. A first gate dielectric layer is disposed between the select gate and the stacked gate structure. A second gate dielectric layer is disposed between the select gate and the substrate. A shallow doped region is disposed in the substrate under the stacked gate structure and the select gate. A deep doped region is disposed in the substrate on one side of the stacked gate structure. The conductive plug on the substrate extends through the drain region and the deep doped region.Type: ApplicationFiled: May 17, 2007Publication date: September 20, 2007Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Wei-Zhe Wong, Ching-Sung Yang
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Patent number: 7235839Abstract: A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked gate structure. A select gate is disposed between the stacked gate structure and the source region. A first gate dielectric layer is disposed between the select gate and the stacked gate structure. A second gate dielectric layer is disposed between the select gate and the substrate. A shallow doped region is disposed in the substrate under the stacked gate structure and the select gate. A deep doped region is disposed in the substrate on one side of the stacked gate structure. The conductive plug on the substrate extends through the drain region and the deep doped region.Type: GrantFiled: November 25, 2004Date of Patent: June 26, 2007Assignee: Powerchip Semiconductor Corp.Inventors: Wei-Zhe Wong, Ching-Sung Yang
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Publication number: 20070085124Abstract: A non-volatile memory device having a substrate, an n type well, a p type well, a control gate, a composite dielectric layer, a source region and a drain region is provided. A trench is formed in the substrate. The n type well is formed in the substrate, The p type well is formed in the substrate above the n type well. The junction of p type well and the n type well is higher than the bottom of the trench. The control gate which protruding the surface of substrate is formed on the sidewalls of the trench. The composite dielectric layer is formed between the control gate and the substrate. The composite dielectric layer includes a charge-trapping layer. The source region and the drain region are formed in the substrate of the bottom of the trench respectively next to the sides of the control gate.Type: ApplicationFiled: November 10, 2006Publication date: April 19, 2007Inventors: Wei-Zhe Wong, Ching-Sung Yang, Chih-Chen Cho