Abstract: Some of the embodiments of the present disclosure provide a semiconductor package interposer comprising a substrate having a first surface and a second surface, a plurality of vias extending between the first surface and the second surface of the substrate, the plurality of vias electrically connecting electrical connectors or circuitry on the first surface of the substrate to electrical connectors or circuitry on the second surface of the substrate, and metal plugs at least partially filling the plurality of vias. At least one of (i) the first surface or (ii) the second surface of the substrate includes depressions at distal ends of the metal plugs.

Abstract: Embodiments provide a packaging arrangement that includes a high density interconnect bridge for interconnecting dies within the packaging arrangement. The packaging arrangement comprises one or more redistribution layers and an interconnect bridge embedded within the one or more redistribution layers. A first die is coupled to (i) a first portion of the one or more redistribution layers and (ii) a first portion of the interconnect bridge. A second die coupled to a (ii) a second portion of the one or more redistribution layers and (ii) a second portion of the interconnect bridge to electrically couple the first die and the second die via at least the first interconnect bridge.

Abstract: A read voltage level estimating method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a first region of a rewritable non-volatile memory module according to a first read voltage level to obtain a first encoding unit which belongs to a block code; performing a first decoding procedure on the first encoding unit and recording first decoding information; reading the first region according to a second read voltage level to obtain a second encoding unit which belongs to the block code; performing a second decoding procedure on the second encoding unit and recording second decoding information; and estimating and obtaining a third read voltage level according to the first decoding information and the second decoding information. Accordingly, a management ability of the rewritable non-volatile memory module adopting the block code may be improved.

Abstract: A method for access control of data in a filesystem is provided. The method includes storing a map in a server, the map coupled to an agent, the map associating access control rules, filenames in a namespace in a first filesystem, and owners of files. The method includes determining a block filename in a namespace in a second filesystem, based on an I/O request from a data node to the second filesystem regarding a data block. The method includes determining a username of the I/O request and determining a filename in the namespace in the first filesystem, based on the block filename in the namespace in the second filesystem. The method includes applying to the data block and the username an access control rule that the map associates with an owner of a file having the filename in the namespace in the first filesystem.

Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.

Abstract: An intervertebral implant is a porous structure formed of a plurality of metal balls, and the intervertebral implant includes a bone support area and a bone growth area. The bone support area and the bone growth area each have a plurality of connecting holes, and a porosity of the bone support area is smaller than that of the bone growth area.

Abstract: An apparatus, a system and a method for space status detection based on acoustic signal are provided. The detecting apparatus includes an audio transmitting device, an audio receiving device, a signal processing device and a decision device. The audio transmitting device transmits an acoustic signal into a space. The audio receiving device receives a varied acoustic signal as a sensing signal. The signal processing device is coupled to the audio receiving device to receive the sensing signal and generates a characteristic parameter of a space status according to the sensing signal. The decision device is coupled to the signal processing device to receive the characteristic parameter and detects a change of the space status according to the characteristic parameter.

Abstract: A data reading method is provided. The data reading method includes receiving a read command from a host system; sending a first read command sequence to obtain a first data string from memory cells of a rewritable non-volatile memory module; performing a decoding procedure on the first data string to generate a decoded first data string; and, if there is an error bit in the decoded first data string, sending a second read command sequence to obtain a second data string from the memory cells, performing a logical operation on the decoded first data string and the second data string to obtain an adjusting data string, adjusting the decoded first data string according to the adjusting data string to obtain an adjusted first data string, and using a data string obtained after re-performing the decoding procedure on the adjusted first data string as the decoded first data string.

Abstract: A memory control circuit unit including a plurality of data randomizer circuits and a data selection circuit is provided. When a first data stream is received from a host system, the first data stream is input into the data randomizer circuits to respectively output a plurality of second data streams. The data selection circuit selects one of the second data streams as a third data stream according to contents of the second data streams, and the third data stream is programmed into a rewritable non-volatile memory module. Accordingly, data written into the rewritable non-volatile memory module can be effectively disarranged.

Abstract: A surgical template positioning device is provided, and has a template and a dental mold. The template has a first surface formed with at least three spherical recesses, a second surface, and a guiding hole. The dental mold has at least three spherical portions partially embedded in the at least three spherical recesses and an implanted hole having an axis the same as the guiding hole. The at least three spherical recesses have three spherical centers as being three vertices of a triangle, the axis passes through the triangle, and the at least three spherical portions have spherical centers corresponding with the three vertices of the triangle. A method of manufacturing the surgical positioning device is also provided.

Abstract: A stabilizer including a first component and a second component. The first component is a compound represented by the formula (1). The second component is a compound represented by the formula (2).

Abstract: A growth method of dendritic crystal structure that provides directional heat transfer, including the steps: A. providing a substrate, whereby the substrate is provided with a plurality of crystal defects; B. depositing a plurality of metal ions on the substrate using a deposition method, whereby the metal ions on the crystal defects enable the growth of dendritic crystals. Moreover, an interspace is provided between each of the dendritic crystals. Hence, when the substrate is in contact with a heat source, heat energy is transferred from the substrate in the growth direction of the dendritic crystals; or, when the dendritic crystals are disposed at the position of a heat source, heat provided by the heat source is transferred from the dendritic crystals in a direction toward the substrate. Accordingly, the fractal structure of the dendritic crystals is used to provide ample heat dissipation areas and contact areas.

Abstract: A data programming method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving first data and programming the first data into a first lower physical programming unit; receiving second data; in response to the second data to be programmed into a first upper physical programming unit corresponding to the first lower physical programming unit, performing a first data obtaining operation which does not include reading the first lower physical programming unit by using a default read voltage; and programming the second data into the first upper physical programming unit according to the third data obtained through the first data obtaining operation.

Abstract: A decoding method, a memory storage device and a memory controlling circuit are provided. The decoding method includes: sending a read command sequence configured to read the memory cells, so as to obtain a plurality of first verification bits; executing a first decoding procedure according to the first verification bits, and determining whether a first valid codeword is generated; if the first valid codeword is not generated, sending another read command sequence configured to obtain a plurality of second verification bits; calculating a total number of the memory cells conforming to a specific condition according to the second verification bits; obtaining a channel reliability message according to the total number; and executing a second decoding procedure according to the channel reliability message. Accordingly, a correcting ability of decoding may be improved.

Abstract: A method of manufacturing a semiconductor structure, comprising: receiving a first substrate including a first surface, a second surface opposite to the first surface and a plurality of conductive bumps disposed over the first surface; receiving a second substrate; disposing an adhesive over the first substrate or the second substrate; heating the adhesive in a first ambiance; bonding the first substrate with the second substrate by applying a force of less than about 10,000N upon the first substrate or the second substrate and heating the adhesive in a second ambiance; and thinning down a thickness of the first substrate from the second surface.

Abstract: The instant invention provides a fitness equipment for facilitating both push up and wriggling excises without occupying a large storage space. The instant invention discloses a push-up twisting plate; which is made up of two circular, rotating bases and each base has a detachable handle. The handles can be easily removed by the user by applying a rotational force on the handle and an opposing rotational force on the base. To assemble the push-up twisting plate, the user can repeat the same motion, but in reverse.

Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a plurality of first memory cells according to a first soft-decision read voltage level to obtain a first soft-decision coding unit belonging to a block code; performing a first soft-decision decoding procedure for the first soft-decision coding unit; if the first soft-decision decoding procedure fails, reading the first memory cells according to a second soft-decision read voltage level to obtain a second soft-decision coding unit belonging to the block code, where a difference value between the first soft-decision read voltage level and the second soft-decision read voltage level is related to a wear degree of the first memory cells; and performing a second soft-decision decoding procedure for the second soft-decision coding unit. Accordingly, a decoding efficiency of block codes may be improved.

Abstract: A manufacturing and separating device and a method for oily radioactive substances provide an automatic synthesis box to minimize the man-made errors during the manufacturing, such that mass production for the oily radioactive substance can be possible, the radiation exposure time of the manufacturing staff can be reduced, and the radioactivity of the final products can be detected. The manufacturing and separating device includes a first reaction material bottle, a first heating device, a gas pump, a first flushing material bottle, a second flushing material bottle, a purifying device, a first transmission unit, a temperature-controlled temporary storage tank, a filter, a first collection bottle, a second collection bottle, a plurality of valves and a control unit.

Abstract: A method of forming an integrated circuit comprises forming a first doped region in a substrate using a first angle ion implantation performed on a first side of a gate structure. The gate structure has a length in a first direction and a width in a second direction. The method also comprises forming a second doped region in the substrate using a second angle ion implantation performed on a second side of the gate structure. The first angle ion implantation has a first implantation angle with respect to the second direction and the second angle ion implantation has a second implantation angle with respect to the second direction. Each of the first implantation angle and the second implantation angle is substantially larger than 0° and less than 90°.

Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.