Abstract: A method of generating an IC layout diagram includes generating a plurality of logic patterns, wherein each logic pattern corresponds to a number of bits N greater than two, arranging a column of NOR-type read-only memory (ROM) bit cells as a plurality of N-bit groups separated from each other by isolation features, assigning a pattern of the plurality of logic patterns to each N-bit group of the plurality of N-bit groups, and storing an IC layout diagram including the plurality of logic patterns in a storage device.

Abstract: A memory includes first, second, third and fourth banks stacked on each other relative to a first direction and correspondingly including memory cells. Each of first to fourth banks includes first and second partitions separated from each other by a local access manager relative to the first direction. The (A) the first and second banks and (B) the third and fourth banks are organized as corresponding first and second bundles. The memory further includes a global access manager separating the first and second bundles relative to the first direction. The global access manager being separately coupled to the first and second bundles by corresponding first and second bundle-wide write lines or corresponding first and second bundle-wide read lines. The global access manager is configured to selectively access the first and second bundles on a mutually exclusive basis.

Abstract: A memory device is provided, including at least one inverter, a transistor coupled between the at least one inverter and a bit line, and an assist circuit coupled to the bit line, configured to provide a negative voltage to the bit line, and configured to pull down a power supply voltage provided to the at least one inverter.

Abstract: A memory device includes: a first array of memory cells; a second array of tracking cells, the second array being configured to emulate the first array; a first word line coupled to corresponding ones of the memory cells in a corresponding one of rows of the first array and to the tracking cells; a second word line configured to emulate the first word line; a first adjust circuit coupled to the first word line; a second adjust circuit coupled to the second word line; and an adjust-timing circuit coupled to the second adjust circuit.

Abstract: A memory circuit includes a first and second inverter, and a level shifter circuit. The first inverter is coupled to a first voltage supply, and configured to generate a first input signal in response to a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured generate a first and second signal responsive to a first or second input signal. The second inverter is configured to generate a word line signal in response to the first signal. The level shifter circuit is configured to delay a leading edge of the word line signal in response to the first or second signal. An amount of delay of the leading edge of the word line signal is based on a voltage difference between the first and second supply voltage. The first supply voltage has a first swing. The second supply voltage has a second swing.

Abstract: A memory device is provided, including at least one inverter, a transistor coupled between the at least one inverter and a bit line, and an assist circuit coupled to the bit line, configured to provide a negative voltage to the bit line, and configured to pull down a power supply voltage provided to the at least one inverter.

Abstract: A method of generating an IC layout diagram includes dividing a column of NOR-type read-only memory (ROM) bit cells into a plurality of N-bit groups separated by isolation features, wherein each group includes the number of bits N greater than two, based on a ROM code programming pattern of the column, assigning one or more logic patterns to each N-bit group of the plurality of N-bit groups, and storing an IC layout diagram including the logic patterns in a storage device.

Abstract: A memory device includes memory cells formed on a first side of a substrate and powered by a supply voltage; a third metallization layer formed on the first side and including third metal tracks, at least one of the third metal tracks configured to only carry a non-power signal instead of carrying the supply voltage; a fourth metallization layer formed on the first side and including fourth metal tracks, each configured only as a word line; a fifth metallization layer formed on a second side of the substrate and including fifth metal tracks, each configured to carry the supply voltage or a ground voltage; and a sixth metallization layer formed on the second side and including sixth metal tracks, each configured to carry the supply voltage or the ground voltage.

Abstract: A memory device includes a memory array comprising a plurality of word lines, the plurality of word lines operatively coupled to a plurality of sets of memory cells, respectively. The memory device includes a controller operatively coupled to the memory array, and comprising an adaptive tracking circuit. The adaptive tracking circuit is configured to: receive a first signal conducted through a first tracking line; receive an address signal indicating one of the word lines to be asserted; and adjust, based on the address signal, a timing of a transition edge of a second signal conducted through a second tracking line.

Abstract: A method includes: turning on a first switch coupled between a first array of memory and a voltage supply according to a first charge signal; turning on a second switch coupled between a second array of memory and the voltage supply according to a second charge signal different from the first charge signal; and generating the first charge signal and the second charge signal according to a word line address. The second array of memory is located between the second switch and the first array of memory.

Abstract: A semiconductor device includes a bit line pre-charger and a buffer circuit. The bit line pre-charger is configured to charge at least one bit line when a first control signal has a first voltage level. The buffer circuit is configured to generate the first control signal. During a first standby period, the buffer circuit adjusts the first control signal to a second voltage level different from the first voltage level.

Abstract: An integrated circuit includes integrated circuit includes a memory bank, a first group of word lines, a second group of word lines, an access circuit, a converter circuit and a decoder circuit. The first group of word lines is coupled to the memory bank. The second group of word lines is coupled to the memory bank, and arranged in order with the first group of word lines. The access circuit is configured to read the memory bank. The converter circuit is configured to control the access circuit at least based on a first control signal. The decoder circuit is configured to generate the first control signal at least according to a first bit and a second bit of an address signal. The first bit and the second bit indicates one group of the first group of word lines and the second group of word lines.

Abstract: A semiconductor device includes: a first array of memory cells; a second array of tracking cells, the second array being configured to emulate the first array; a first word line coupled to corresponding ones of the memory cells in a corresponding one of rows of the first array and to the tracking cells; a second word line configured to emulate the first word line; a first adjust circuit coupled to the first word line; and a second adjust circuit coupled to the second word line.

Abstract: A circuit includes a memory circuit, and a power management circuit having a latch circuit. The latch circuit, in response to a first state of a first management signal, controls supply of a first supply voltage to the memory circuit in accordance with a control signal. The latch circuit, in response to a second state of the first management signal, stores a state of the control signal, and controls supply of the first supply voltage in accordance with the stored state. The power management circuit, in response to a second management signal, disables at least one interface circuit in at least one of the power management circuit or the memory circuit. The at least one interface circuit interfaces between a first power domain of a first power supply voltage corresponding to the first supply voltage, and a second power domain of a different second power supply voltage.

Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device.

Abstract: A memory device includes a memory array comprising a plurality of word lines, the plurality of word lines operatively coupled to a plurality of sets of memory cells, respectively. The memory device includes a controller operatively coupled to the memory array, and comprising an adaptive tracking circuit. The adaptive tracking circuit is configured to: receive a first signal conducted through a first tracking line; receive an address signal indicating one of the word lines to be asserted; and adjust, based on the address signal, a timing of a transition edge of a second signal conducted through a second tracking line.

Abstract: A memory circuit includes a first and second inverter, a level shifter circuit, a memory cell configured to receive a word line signal, and a local input/output (LIO) circuit. The first inverter is coupled to a first voltage supply, and configured to generate a first input signal in response to a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured generate a first and second signal responsive to a first or second input signal. The second inverter is configured to generate the word line signal in response to the first signal. The level shifter circuit is configured to delay a leading edge of the word line signal in response to the first or second signal. An amount of delay of the leading edge of the word line signal is based on a voltage difference between the first and second supply voltage.

Abstract: A memory circuit includes a control circuit coupled to the word line driver circuit. The control circuit is configured to delay a leading or falling edge of a word line signal in response to at least a first clock signal. The control circuit includes a first clock circuit configured to generate a second clock signal in response to a first reset signal and a clock signal, and an adjustable delay circuit configured to adjust a delay between the second and third clock signal in response to the second clock signal and an enable signal. The third clock signal is a delayed version of the second clock signal. An amount of the delay between the second and third clock signal is based on a voltage difference between a first supply voltage having a first swing, and a second supply voltage having a second swing.

Abstract: A memory device is provided and includes a memory array, first to second latch circuits and a gating circuit. Read and write operations are triggered by first and second edges of an internal clock signal respectively. The first latch circuit generates a first output signal in response to an input signal and a first latch clock signal, a first edge of the first latch clock signal generated based on the first edge of the internal clock signal. The second latch circuit generates a second output signal in response to the first output signal and a second latch clock signal, a first edge of the second latch clock signal being between first and second edges of the first latch clock signal. The gating circuit generates, in response to the second output signal and a gating clock generated, a third output signal to the memory array.

Abstract: A memory device is provided, including at least one bit cell, a pair of transistors, and a voltage generation circuit. The voltage generation circuit is coupled to the negative voltage line and is configured to pull down a voltage of at least one of the pair of data lines to a negative voltage level through the negative voltage line. The voltage generation circuit includes a first capacitive unit, a second capacitive unit, and a switch circuit. The first capacitive unit includes a first capacitor. The second capacitive unit includes a second capacitor. The switch circuit is configured to connect the first capacitor, the second capacitor, or the combination thereof to the negative voltage line in response to a first kick signal and a second kick signal that are different from each other.