Patents by Inventor Ching-Wei Wu

Ching-Wei Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230377623
    Abstract: A method includes: turning on a first switch coupled between a first array of memory and a voltage supply according to a first charge signal; turning on a second switch coupled between a second array of memory and the voltage supply according to a second charge signal different from the first charge signal; and generating the first charge signal and the second charge signal according to a word line address. The second array of memory is located between the second switch and the first array of memory.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 23, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li YANG, He-Zhou WAN, Kuan CHENG, Ching-Wei WU
  • Publication number: 20230378939
    Abstract: A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and an enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal. In response to the corresponding disabling logic level of the latched clock signal, the input latch is configured to hold a logic level of the latched output signal unchanged, regardless of the input signal having one or more logic level switchings, while the enable signal is having the disabling logic level.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: XiuLi YANG, Kuan CHENG, He-Zhou WAN, Ching-Wei WU, Wenchao HAO
  • Publication number: 20230368828
    Abstract: A circuit includes a series of a first latch circuit, selection circuit, second latch circuit, and pre-decoder. A control circuit, based on a clock signal, outputs control signals to the selection circuit and first and second latch circuits, and, to the pre-decoder, a pulse signal including a first pulse during a first portion of a clock period in response to a read enable signal having a first logical state, and a second pulse during a second portion of the clock period in response to a write enable signal having the first logical state. Based on the control signals, the selection circuit and first and second latch circuits output read and write addresses to the pre-decoder during the respective first and second clock period portions, and the pre-decoder outputs a partially decoded address in response to each of the read address and first pulse, and the write address and second pulse.
    Type: Application
    Filed: July 18, 2023
    Publication date: November 16, 2023
    Inventors: XiuLi YANG, Ching-Wei WU, He-Zhou WAN, Kuan CHENG, Luping KONG
  • Publication number: 20230368826
    Abstract: A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first P-type transistor coupled to the NAND logic gate, and configured to receive a first clock signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Inventors: Yi-Tzu CHEN, Ching-Wei WU, Hau-Tai SHIEH, Hung-Jen LIAO, Fu-An WU, He-Zhou WAN, XiuLi YANG
  • Patent number: 11811404
    Abstract: A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and a first enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the first enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal. The latch clock generator includes a first inverter configured to generate an inverted signal of the first enable signal, and a NAND gate coupled to the first inverter to receive the inverted signal of the first enable signal. The NAND gate is configured to generate the latched clock signal based on the clock signal and the inverted signal of the first enable signal.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: November 7, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITED
    Inventors: XiuLi Yang, Kuan Cheng, He-Zhou Wan, Ching-Wei Wu, Wenchao Hao
  • Publication number: 20230342272
    Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device.
    Type: Application
    Filed: June 28, 2023
    Publication date: October 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hung CHANG, Atul KATOCH, Chia-En HUANG, Ching-Wei WU, Donald G. MIKAN, JR., Hao-I YANG, Kao-Cheng LIN, Ming-Chien TSAI, Saman M.I. ADHAM, Tsung-Yung CHANG, Uppu Sharath CHANDRA
  • Publication number: 20230326501
    Abstract: A memory device includes a memory array, a first latch and a first logic element. The memory array is configured to operate according to a first global write signal. The first latch is configured to generate a first latch write data based on a clock signal. The first logic element is configured to generate the first global write signal based on the clock signal and the first latch write data.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 12, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC Nanjing Company Limited, TSMC China Company Limited
    Inventors: He-Zhou WAN, Xiu-Li YANG, Pei-Le LI, Ching-Wei WU
  • Patent number: 11776622
    Abstract: A circuit includes first and second bit lines, a second power node having a voltage level below that of a first power node, a reference node having a reference voltage level, first and second pass gates and drivers, first and second logic gates coupled to the second power node, first and second conversion circuits coupled between the first power node and respective first and second logic and pass gates, and first and second NOR gates coupled between the second power node and respective first and second logic gates and drivers. The first and second pass gates selectively couple the first and second bit lines to the first power node responsive to the respective second and first logic gates and conversion circuits, and the first and second drivers selectively couple the first and second bit lines to the reference node responsive to the respective first and second logic and NOR gates.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pankaj Aggarwal, Ching-Wei Wu, Jaymeen Bharatkumar Aseem
  • Patent number: 11769539
    Abstract: An integrated circuit includes multiple memory cells, a first pair of complementary data lines, a second pair of complementary data lines, multiple first word lines, and multiple second word lines. The memory cells include a first array of memory cells and a second array of memory cells. The first pair of complementary data lines are coupled to the first array of memory cells. The second pair of complementary data lines are coupled to the second array of memory cells. Lengths of the first pair of complementary data lines are shorter than lengths of the second pair of complementary data lines. The first word lines and the second word lines are arranged according to a predetermined ratio of a number of the first word lines to a number of the second word lines. The predetermined ratio is less than 1.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: September 26, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li Yang, He-Zhou Wan, Kuan Cheng, Ching-Wei Wu
  • Publication number: 20230290395
    Abstract: An integrated circuit includes integrated circuit includes a memory bank, a first group of word lines, a second group of word lines, an access circuit, a converter circuit and a decoder circuit. The first group of word lines is coupled to the memory bank. The second group of word lines is coupled to the memory bank, and arranged in order with the first group of word lines. The access circuit is configured to read the memory bank. The converter circuit is configured to control the access circuit at least based on a first control signal. The decoder circuit is configured to generate the first control signal at least according to a first bit and a second bit of an address signal. The first bit and the second bit indicates one group of the first group of word lines and the second group of word lines.
    Type: Application
    Filed: May 18, 2023
    Publication date: September 14, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li YANG, He-Zhou WAN, Kuan CHENG, Ching-Wei WU
  • Publication number: 20230267989
    Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.
    Type: Application
    Filed: April 25, 2023
    Publication date: August 24, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao
  • Patent number: 11734142
    Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: August 22, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hung Chang, Atul Katoch, Chia-En Huang, Ching-Wei Wu, Donald G. Mikan, Jr., Hao-I Yang, Kao-Cheng Lin, Ming-Chien Tsai, Saman M. I. Adham, Tsung-Yung Chang, Uppu Sharath Chandra
  • Patent number: 11721374
    Abstract: A memory device includes a local input/output circuit and a main input/output circuit. The local input/output circuit is configured to generate a first local write signal based on a first global write signal and a second global write signal, and configured to transmit the first local write signal to a plurality of first bit lines. The main input/output circuit include a first latch and logic elements. The first latch is configured to generate a first bit write mask signal based on a clock signal. The logic elements are configured to generate the first global write signal and the second global write signal based on the clock signal and the first bit write mask signal.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: August 8, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: He-Zhou Wan, Xiu-Li Yang, Pei-Le Li, Ching-Wei Wu
  • Patent number: 11715505
    Abstract: A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a second N-type transistor coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: August 1, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITED
    Inventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao, Fu-An Wu, He-Zhou Wan, XiuLi Yang
  • Patent number: 11705174
    Abstract: An integrated circuit includes a plurality of memory cells, a first pair of complementary data lines, and a second pair of complementary data lines. The plurality of memory cells include a first array of memory cells and a second array of memory cells. The first pair of complementary data lines are coupled to the first array of memory cells. The second pair of complementary data lines are different from the first pair of complementary data lines and are coupled to the second array of memory cells. A number of memory cells in the first array of memory cells is different from a number of memory cells in the second array of memory cells.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: July 18, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li Yang, He-Zhou Wan, Kuan Cheng, Ching-Wei Wu
  • Patent number: 11705175
    Abstract: A circuit includes a plurality of registers, each register including SRAM cells, a read port configured to receive a read address, a write port configured to receive a write address, a selection circuit, a latch circuit, and a decoder coupled in series between the read and write ports and the plurality of registers, and a control circuit. Responsive to a clock signal and read and write enable signals, the control circuit causes the selection circuit, the latch circuit, and the decoder to select a first register of the plurality of registers in a read operation based on the read address, and select a second register of the plurality of registers in a write operation based on the write address.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: July 18, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED, TSMC CHINA COMPANY, LIMITED
    Inventors: XiuLi Yang, Ching-Wei Wu, He-Zhou Wan, Kuan Cheng, Luping Kong
  • Patent number: 11670362
    Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: June 6, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao
  • Patent number: 11651134
    Abstract: A method includes specifying a target memory macro, and determining failure rates of function-blocks in the target memory macro based on an amount of transistors and area distributions in a collection of base cells. The method also includes determining a safety level of the target memory macro, based upon a failure-mode analysis of the target memory macro, from a memory compiler, based on the determined failure rate.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: May 16, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY, LIMITED
    Inventors: Ching-Wei Wu, Ming-En Bu, He-Zhou Wan, Hidehiro Fujiwara, Xiu-Li Yang
  • Publication number: 20230114646
    Abstract: A circuit includes a power management circuit configured to receive at least a first or a second control signal, and to supply at least a first, second or a third supply voltage. The first control signal has a first voltage swing. The second control signal has a second voltage swing. The power management circuit includes a first level shifter circuit configured to generate a first level shifted signal in response to the first control signal, and a first header circuit coupled to at least the first level shifter circuit, a first voltage supply and a second voltage supply. The first header circuit is configured to supply the first supply voltage of the first voltage supply to the first node in response to the first control signal, and to supply the second supply voltage of the second voltage supply to the second node in response to the first level shifted signal.
    Type: Application
    Filed: December 15, 2022
    Publication date: April 13, 2023
    Inventors: Xiu-Li YANG, Ching-Wei WU, He-Zhou WAN, Ming-En BU
  • Patent number: 11545191
    Abstract: A circuit includes a power management circuit and a memory circuit. The power management circuit is configured to receive a first control signal and a second control signal, and to supply a first supply voltage, a second supply voltage and a third supply voltage. The first control signal has a first voltage swing, and the second control signal has a second voltage swing different from the first voltage swing. The first control signal causes the power management circuit to enter a power management mode having a first state and a second state. The memory circuit is coupled to the power management circuit, and is in the first state or the second state in response to at least the first supply voltage supplied by the power management circuit.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: January 3, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY. LIMITED
    Inventors: Xiu-Li Yang, Ching-Wei Wu, He-Zhou Wan, Ming-En Bu