Patents by Inventor Ching-Wen Hsiao

Ching-Wen Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor package assembly
    Patent number: 9704836
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace disposed at a first layer-level. A second conductive trace is disposed at a second layer-level. A first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer, which is beside the first inter-metal dielectric (IMD) layer, are disposed between the first conductive trace and the second conductive trace.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: July 11, 2017
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Ching-Wen Hsiao
  • Package structures and methods for forming the same
    Patent number: 9679836
    Abstract: A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A solder region is disposed in the polymer region and electrically coupled to the redistribution line. The solder region includes a second flat top surface not higher than the first flat top surface.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: June 13, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Wen Hsiao, Ming-Da Cheng, Chih-Wei Lin, Chen-Shien Chen, Chih-Hua Chen, Chen-Cheng Kuo
  • Alignment mark design for packages
    Patent number: 9666522
    Abstract: A package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment mark penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Hsien Huang, Hsien-Wei Chen, Ching-Wen Hsiao, Der-Chyang Yeh, Shin-Puu Jeng, Chen-Hua Yu
  • FOLDABLE STATUE BAG
    Publication number: 20170137181
    Abstract: A foldable statue bag is disclosed. The foldable statue bag comprises a foldable bag body with an opening on a top end, and a statue integrated with the foldable bag body. The foldable bag body has two adjacent surfaces connect to a first fold line at opposite sides to form a recess or a protrusion, and the statue has a second fold line for folding so that the statue is received in the recess or protrude from the protrusion when the foldable bag body is folded, and the statue is expanded to form a three dimensional decoration when the foldable bag body is unfolded.
    Type: Application
    Filed: November 16, 2016
    Publication date: May 18, 2017
    Applicant: Fun Chain Co., Ltd.
    Inventors: Min Chun Liao, Ching Wen Hsiao, Hsin Yi Lu
  • Packaging mechanisms for dies with different sizes of connectors
    Patent number: 9646894
    Abstract: Embodiments of mechanisms for forming a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate. The usage of the interconnect substrate enables cost reduction because it is cheaper to make than an interposer with through silicon vias (TSVs). The interconnect substrate also enables dies with different sizes of bump structures to be packaged in the same die package.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: May 9, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hua Chen, Chen-Shien Chen, Ching-Wen Hsiao
  • Semiconductor Device with Discrete Blocks
    Publication number: 20170125386
    Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.
    Type: Application
    Filed: January 9, 2017
    Publication date: May 4, 2017
    Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Wei Sen Chang, Shou-Cheng Hu
  • FAN-OUT WAFER LEVEL PACKAGE STRUCTURE
    Publication number: 20170098589
    Abstract: A semiconductor package structure is provided. The structure includes a molding compound having a dicing lane region. A semiconductor die is disposed in the molding compound and surrounded by the dicing lane region. The semiconductor die has a first surface and a second surface opposite thereto, and the first and second surfaces are exposed from the molding compound. The structure further includes a redistribution layer (RDL) structure disposed on the first surface of the semiconductor die and covering the molding compound. The RDL structure includes a photo-sensitive material and has an opening aligned with the dicing lane region.
    Type: Application
    Filed: July 15, 2016
    Publication date: April 6, 2017
    Inventors: Nai-Wei LIU, Tzu-Hung LIN, I-Hsuan PENG, Ching-Wen HSIAO, Wei-Che HUANG
  • SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20170098628
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor body and a conductive structure disposed below the semiconductor body. The semiconductor package structure also includes an insulating layer surrounding the conductive structure. The semiconductor package structure further includes a redistribution layer structure coupled to the conductive structure. In addition, the semiconductor package structure includes a molding compound surrounding the semiconductor body. A portion of the molding compound extends between the redistribution layer structure and the semiconductor body.
    Type: Application
    Filed: July 15, 2016
    Publication date: April 6, 2017
    Inventors: Nai-Wei LIU, Tzu-Hung LIN, I-Hsuan PENG, Ching-Wen HSIAO, Wei-Che HUANG
  • STACKED FAN-OUT PACKAGE STRUCTURE
    Publication number: 20170098629
    Abstract: A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.
    Type: Application
    Filed: July 25, 2016
    Publication date: April 6, 2017
    Inventors: Nai-Wei LIU, Tzu-Hung LIN, I-Hsuan PENG, Ching-Wen HSIAO, Wei-Che HUANG
  • Package-on-package (PoP) device with integrated passive device in a via
    Patent number: 9613917
    Abstract: A package for a use in a package-on-package (PoP) device. The package includes a substrate, a polymer layer formed on the substrate, a first via formed in the polymer layer, and a material disposed in the first via to form a first passive device. The material may be a high dielectric constant dielectric material in order to form a capacitor or a resistive material to form a resistor.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Wen Hsiao, Chen-Shien Chen
  • Copper bump joint structures with improved crack resistance
    Patent number: 9607936
    Abstract: An integrated circuit structure includes a first work piece and a second work piece. The first work piece includes a semiconductor substrate, and a copper bump over the semiconductor substrate. The second work piece includes a bond pad. A solder is between and adjoining the first work piece and the second work piece, wherein the solder electrically connects the copper bump to the bond pad. The solder includes palladium.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: March 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Wen Hsiao, Jiun Yi Wu, Ru-Ying Huang, Chen-Shien Chen
  • FAN-OUT PACKAGE STRUCTURE HAVING EMBEDDED PACKAGE SUBSTRATE
    Publication number: 20170077073
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first semiconductor package that includes a first semiconductor die having a first surface and a second surface opposite thereto. A first package substrate is disposed on the first surface of the first semiconductor die. A first molding compound surrounds the first semiconductor die and the first package substrate. A first redistribution layer (RDL) structure is disposed on the first molding compound, in which the first package substrate is interposed and electrically coupled between the first semiconductor die and the first RDL structure.
    Type: Application
    Filed: July 6, 2016
    Publication date: March 16, 2017
    Inventors: Tzu-Hung LIN, Chi-Chin LIEN, Nai-Wei LIU, I-Hsuan PENG, Ching-Wen HSIAO, Wei-Che HUANG
  • Warpage Control of Semiconductor Die Package
    Publication number: 20170069594
    Abstract: Various embodiments of mechanisms for forming a die package using a compressive dielectric layer to contact and to surround through substrate vias (TSVs) in the die package are provided. The compressive dielectric layer reduces or eliminates bowing of the die package. As a result, the risk of broken redistribution layer (RDL) due to bowing is reduced or eliminated. In addition, the compressive dielectric layer, which is formed between the conductive TSV columns and surrounding molding compound, improves the adhesion between the conductive TSV columns and the molding compound. Consequently, the reliability of the die package is improved.
    Type: Application
    Filed: November 17, 2016
    Publication date: March 9, 2017
    Inventors: Kuo Lung Pan, Ching-Wen Hsiao, Chen-Shien Chen
  • STRUCTURE AND LAYOUT OF BALL GRID ARRAY PACKAGES
    Publication number: 20170053884
    Abstract: A ball grid array for an integrated circuit package includes an array of connection points derived from a base unit of hexagonal pattern repeated in at least one or more sections of the integrated circuit package. According to one embodiment, the connection points are solder balls mounted on a lower surface of the integrated circuit package.
    Type: Application
    Filed: June 14, 2016
    Publication date: February 23, 2017
    Inventors: Tzu-Hung Lin, Ching-Wen Hsiao, I-Hsuan Peng, Nai-Wei Liu
  • Package structures including a capacitor and methods of forming the same
    Patent number: 9576821
    Abstract: A package includes a die, an encapsulant, and a capacitor. The package has a package first side and a package second side. The die has a die first side corresponding to the package first side, and has a die second side corresponding to the package second side. The die first side is opposite the die second side. The encapsulant surrounds the die. The capacitor includes a first plate and a second plate in the encapsulant, and opposing surfaces of the first plate and the second plate extend in a direction from the package first side to the package second side. The external conductive connectors are attached to at least one of the package first side and the package second side.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sut-I Lo, Ching-Wen Hsiao, Hsu-Hsien Chen, Chen-Shien Chen
  • SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20170033079
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first electronic component on a substrate. The semiconductor package structure also includes a second electronic component stacked on the first electronic component. The active surface of the first electronic component faces the active surface of the second electronic component. The semiconductor package structure further includes a molding compound on the first electronic component and surrounding the second electronic component. In addition, the semiconductor package structure includes a third electronic component stacked on the second electronic component and the molding compound.
    Type: Application
    Filed: June 16, 2016
    Publication date: February 2, 2017
    Inventors: Tzu-Hung LIN, Ching-Wen HSIAO, I-Hsuan PENG
  • Semiconductor device with discrete blocks
    Patent number: 9543278
    Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: January 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Wei Sen Chang, Shou-Cheng Hu
  • Warpage control of semiconductor die package
    Patent number: 9508674
    Abstract: Various embodiments of mechanisms for forming a die package using a compressive dielectric layer to contact and to surround through substrate vias (TSVs) in the die package are provided. The compressive dielectric layer reduces or eliminates bowing of the die package. As a result, the risk of broken redistribution layer (RDL) due to bowing is reduced or eliminated. In addition, the compressive dielectric layer, which is formed between the conductive TSV columns and surrounding molding compound, improves the adhesion between the conductive TSV columns and the molding compound. Consequently, the reliability of the die package is improved.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo Lung Pan, Ching-Wen Hsiao, Chen-Shien Chen
  • SEMICONDUCTOR PACKAGE ASSEMBLY AND METHOD FOR FORMING THE SAME
    Publication number: 20160343685
    Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die. The semiconductor package assembly also includes a second semiconductor package bonded to the first semiconductor package. The second semiconductor package includes a second semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. A second RDL structure is coupled to the second semiconductor die. The first RDL structure is positioned between the first semiconductor die and the second RDL structure.
    Type: Application
    Filed: March 16, 2016
    Publication date: November 24, 2016
    Inventors: Tzu-Hung LIN, Ching-Wen HSIAO, I-Hsuan PENG
  • SEMICONDUCTOR PACKAGE ASSEMBLY AND METHOD FOR FORMING THE SAME
    Publication number: 20160343695
    Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die and includes a first conductive trace. The semiconductor package assembly also includes a second semiconductor package bonded to the first semiconductor package. The second semiconductor package includes a second semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. A second RDL structure is coupled to the second semiconductor die and includes a second conductive trace. The first conductive trace is in direct contact with the second conductive trace.
    Type: Application
    Filed: March 16, 2016
    Publication date: November 24, 2016
    Inventors: Tzu-Hung LIN, Ching-Wen HSIAO, I-Hsuan PENG