Abstract: A discrete Through-Assembly Via (TAV) module includes a substrate, and vias extending from a surface of the substrate into the substrate. The TAV module is free from conductive features in contact with one end of each of the conductive vias.

Abstract: A system and method for providing an integrated inductor with a high Quality factor (Q) is provided. An embodiment comprises a magnetic core that is in a center of a conductive spiral. The magnetic core increases the inductance of the integrated inductor to allow the inductor to be used in applications such as a RF choke. The magnetic core may be formed in the same manner and time as an underbump metallization.

Abstract: A package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment mark penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via.

Abstract: A method of forming a die package includes forming a conductive column over a first side of a carrier, attaching a semiconductor die to the first side of the carrier, and forming a molding compound over the first side of the carrier. The semiconductor die and the conductive column are embedded in the molding compound. A second side of the carrier opposite the first side is under a compressive stress. The method also includes forming a first compressive dielectric layer over the semiconductor die, the conductive column, and the molding compound, forming a first redistribution layer (RDL) over the first compressive dielectric layer, and forming a first passivation layer over the first RDL.

Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.

Abstract: The present invention provides a portable optical fiber end face polisher that has a probe, a shuttle, a cover and a resilient actuator. The probe has a driving shaft holding a pin having two through holes. The shuttle holds the driving shaft, a supplying reel and a spooling reel. The cover guides the driving shaft to rotate axially and draws a cleaning medium from the supplying reel to pass through the through holes across a probing face of the pin to the spooling reel. The resilient actuator is mounted between a stopping base of the cover and the shuttle to recover the relative positions of the shuttle and the cover.

Abstract: An apparatus includes an integrated circuit having at least one input/output terminal comprising copper formed thereon. A metal cap layer overlies an upper surface of the at least one input/output terminal. A substrate includes at least one conductive trace formed on a first surface, and a metal finish layer overlies a portion of the at least one conductive trace. A lead free solder connection is disposed between the metal cap layer and the metal finish layer, and a first intermetallic compound is disposed at an interface between the metal cap layer and the lead free solder connection. The lead free solder connection has a copper content of less than 0.5 wt. %, and the first intermetallic compound is substantially free of copper.

Abstract: Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost.

Abstract: Packaged semiconductor devices and packaging methods are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and through-vias disposed in a molding compound. A first redistribution layer (RDL) is disposed over a first side of the through-vias, the integrated circuit die, and the molding compound. A second RDL is disposed over a second side of the through-vias, the integrated circuit die, and the molding compound. Contact pads are disposed over the second RDL. An insulating material of the second RDL includes a recess around a perimeter of one of the contact pads.

Abstract: Various embodiments of mechanisms for forming a die package and a package on package (PoP) structure using one or more compressive dielectric layers to reduce warpage are provided. The compressive dielectric layer(s) is part of a redistribution structure of the die package and its compressive stress reduces or eliminates bowing of the die package. In addition, the one or more compressive dielectric layers improve the adhesion between redistribution structure and the materials surrounding the semiconductor die. As a result, the yield and reliability of the die package and PoP structure using the die package are improved.

Abstract: Various embodiments of mechanisms for forming a die package using through sidewall vias (TsVs), which are formed by sawing through substrate via (TSV) in half, at edges of dies described enable various semiconductor dies and passive components be electrically connected to achieve targeted electrical performance. Redistribution structures with redistribution layers (RDLs) are used along with the TsVs to enable the electrical connections. Since the TsVs are away from the device regions, the device regions do not suffer from the stress caused by the TSV formation. In addition, electrical connections between upper and lower dies by the TsVs increases the efficiency of the area utilization of the die package.

Abstract: Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost.

Abstract: A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls.

Abstract: Packaged semiconductor devices and packaging methods are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and through-vias disposed in a molding compound. A first redistribution layer (RDL) is disposed over a first side of the through-vias, the integrated circuit die, and the molding compound. A second RDL is disposed over a second side of the through-vias, the integrated circuit die, and the molding compound. Contact pads are disposed over the second RDL. An insulating material of the second RDL includes a recess around a perimeter of one of the contact pads.

Abstract: A fiber network events measurement apparatus has a laser module alternately generating a pulse signal detecting beam and an FMCW detecting beam. The beams are sent to the fiber network route through a directional coupler. A photo detector receives feedback energy of the beams transmitting in the fiber network route and converts the feedback energy into electronic signals. A mixer uses a frequency difference calculation to obtain a comparison result according to an original and a reflected FMCW signal. The electronic signal is converted into a digital signal by an A/D converter. A signal control unit then obtains a compound trace result including information of characteristic trace and event positions. The compound trace result shows a fiber characteristic trace and event position trace for measuring the fiber network routes.

Abstract: A discrete Through-Assembly Via (TAV) module includes a substrate, and vias extending from a surface of the substrate into the substrate. The TAV module is free from conductive features in contact with one end of each of the conductive vias.

Abstract: A light-emitting diode (LED) element includes a substrate and a GaN layer formed on the substrate. The GaN layer includes a boundary layer including a surface of the GaN opposing the substrate. The surface has a micro-roughening texture and a macro-roughening texture. The boundary layer includes at least one of As, Si, P, Ge, C, B, F, N, Sb, and Xe ions.

Abstract: Methods and apparatus for package on package structures having stud bump through via interconnections. A structure includes an interconnect layer having a plurality of through via assemblies each including at least one stud bump are formed on conductive pads; and encapsulant surrounding the through via assembly, a first redistribution layer formed over a surface of the encapsulant and coupled to the through via assemblies and carrying connectors, and a second redistribution layer over interconnect layer at the other end of the through via assemblies, the through via assemblies extending vertically through the interconnect layer. In an embodiment the interconnect layer is mounted using the connectors to a lower package substrate to form a package on package structure. A first integrated circuit device may be mounted on the second redistribution layer of the interconnect layer. Methods for forming the interconnect layer and the package on package structures are disclosed.

Abstract: A component package and a method of forming are provided. A first component package may include a first semiconductor device having a pair of interposers attached thereto on opposing sides of the first semiconductor device. Each interposer may include conductive traces formed therein to provide electrical coupling to conductive features formed on the surfaces of the respective interposers. A plurality of through vias may provide for electrically connecting the interposers to one another. A first interposer may provide for electrical connections to a printed circuit board or subsequent semiconductor device. A second interposer may provide for electrical connections to a second semiconductor device and a second component package. The first and second component packages may be combined to form a Package-on-Package (“PoP”) structure.

Abstract: The present invention provides a portable optical fiber end face polisher that has a probe, a shuttle, a cover and a resilient actuator. The probe has a driving shaft holding a pin having two through holes. The shuttle holds the driving shaft, a supplying reel and a spooling reel. The cover guides the driving shaft to rotate axially and draws a cleaning medium from the supplying reel to pass through the through holes across a probing face of the pin to the spooling reel. The resilient actuator is mounted between a stopping base of the cover and the shuttle to recover the relative positions of the shuttle and the cover.