Patents by Inventor Ching-Wen Hung

Ching-Wen Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8765546
    Abstract: A method for fabricating fin-shaped field-effect transistor (FinFET) is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure on the substrate; forming a first gate structure on the fin-shaped structure; forming a first epitaxial layer in the fin-shaped structure adjacent to the first gate structure; forming an interlayer dielectric layer on the first gate structure and the first epitaxial layer; forming an opening in the interlayer dielectric layer to expose the first epitaxial layer; forming a silicon cap on the first epitaxial layer; and forming a contact plug in the opening.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: July 1, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Chih-Sen Huang
  • Publication number: 20140162424
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a region; forming a gate structure on the region of the substrate; forming a raised epitaxial layer in the substrate adjacent to two sides of the gate structure; covering a dielectric layer on the gate structure and the raised epitaxial layer; and using a planarizing process to partially remove the dielectric layer and the gate structure such that the surface of the gate structure is even with the surface of the raised epitaxial layer.
    Type: Application
    Filed: February 17, 2014
    Publication date: June 12, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Ching-Wen Hung
  • Publication number: 20140151763
    Abstract: The present invention provides a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate. The present invention further provides a method of making the same.
    Type: Application
    Filed: December 5, 2012
    Publication date: June 5, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao, Chieh-Te Chen
  • Publication number: 20140154852
    Abstract: The present invention provides a method for forming a semiconductor structure having a metal connect. A substrate is provided, and a transistor and a first ILD layer are formed thereon. A first contact plug is formed in the first ILD layer to electrically connect the source/drain region. A second ILD layer and a third ILD layer are formed on the first ILD layer. A first opening above the gate and a second opening above the first contact plug are formed, wherein a depth of the first contact plug is deeper than that of the second opening. Next, the first opening and the second opening are deepened. Lastly, a metal layer is filled into the first opening and the second opening to respectively form a first metal connect and a second metal connect.
    Type: Application
    Filed: December 5, 2012
    Publication date: June 5, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chieh-Te Chen, Feng-Yi Chang, Chih-Sen Huang, Ching-Wen Hung, Ching-Pin Hsu
  • Patent number: 8710596
    Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a region; a gate structure disposed on the region of the substrate; a raised epitaxial layer disposed in the substrate adjacent to two sides of the gate structure, wherein the surface of the raised epitaxial layer is even with the surface of the gate structure.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: April 29, 2014
    Assignee: United Microelectronics Corp.
    Inventor: Ching-Wen Hung
  • Publication number: 20140103402
    Abstract: The present invention provides a semiconductor structure including at least a contact plug. The structure includes a substrate, a transistor, a first ILD layer, a second ILD layer and a first contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor and levels with a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The first contact plug is disposed in the first ILD layer and the second ILD layer and includes a first trench portion and a first via portion, wherein a boundary of the first trench portion and a first via portion is higher than the top surface of the gate. The present invention further provides a method of making the same.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao
  • Publication number: 20130341685
    Abstract: A manufacturing method for a semiconductor device includes providing a substrate having at least a gate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.
    Type: Application
    Filed: June 20, 2012
    Publication date: December 26, 2013
    Inventors: Ling-Chun Chou, I-Chang Wang, Ching-Wen Hung
  • Patent number: 8574978
    Abstract: A method for forming a semiconductor device includes firstly providing a gate structure disposed on a substrate and a first nitride material layer disposed on the gate structure, secondly performing a protective step to modify the first nitride material layer in the presence of oxygen, then forming a second nitride material layer on the substrate, and later performing a removal step to remove the second nitride material layer without substantially slashing the modified first nitride material layer.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: November 5, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Ling-Chun Chou, I-Chang Wang
  • Publication number: 20130273706
    Abstract: A method for forming a semiconductor device includes firstly providing a gate structure disposed on a substrate and a first nitride material layer disposed on the gate structure, secondly performing a protective step to modify the first nitride material layer in the presence of oxygen, then forming a second nitride material layer on the substrate, and later performing a removal step to remove the second nitride material layer without substantially slashing the modified first nitride material layer.
    Type: Application
    Filed: April 11, 2012
    Publication date: October 17, 2013
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Ling-Chun Chou, I-Chang Wang
  • Publication number: 20130171789
    Abstract: A method for manufacturing a semiconductor device includes providing a substrate having a first gate structure and a second gate structure formed thereon; blanketly forming a seal layer covering the first gate structure and the second gate structure on the substrate; performing a first ion implantation to form first light-doped drains (LDDs) in the substrate respectively at two sides of the first gate structure; and performing a second ion implantation to form second LDDs in the substrate respectively at two sides of the second gate structure; wherein at least one of the first ion implantation and the second ion implantation is performed to penetrate through the seal layer.
    Type: Application
    Filed: January 4, 2012
    Publication date: July 4, 2013
    Inventors: Ling-Chun Chou, Shin-Chuan Huang, I-Chang Wang, Ching-Wen Hung, Buo-Chin Hsu, Yi-Han Ye
  • Publication number: 20130089962
    Abstract: A semiconductor process includes the following steps. A substrate is provided. A gate structure is formed on the substrate. A spacer is formed on the substrate beside the gate structure. The spacer includes a first spacer and a second spacer located on the external surface of the first spacer. A first etching process is performed to etch and form at least a recess in the substrate beside the spacer and entirely remove the second spacer. The etching rate of the first etching process to the first spacer is lower than the etching rate of the first etching process to the second spacer. An epitaxial layer is formed in the recess.
    Type: Application
    Filed: October 11, 2011
    Publication date: April 11, 2013
    Inventors: Chung-Fu Chang, Shin-Chuan Huang, Yu-Hsiang Hung, Chia-Jong Liu, Pei-Yu Chou, Jyh-Shyang Jenq, Ling-Chun Chou, I-Chang Wang, Ching-Wen Hung, Ted Ming-Lang Guo, Chun-Yuan Wu
  • Publication number: 20120286376
    Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a region; a gate structure disposed on the region of the substrate; a raised epitaxial layer disposed in the substrate adjacent to two sides of the gate structure, wherein the surface of the raised epitaxial layer is even with the surface of the gate structure.
    Type: Application
    Filed: May 13, 2011
    Publication date: November 15, 2012
    Inventor: Ching-Wen Hung