Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. A substrate with plural metal gates formed thereon is provided, wherein the adjacent metal gates are separated by insulation. A sacrificial layer is formed for capping the metal gates and the insulation, and the sacrificial layer and the insulation are patterned to form at least an opening for exposing the substrate. A silicide is formed corresponding to the opening at the substrate, and a conductive contact is formed in the opening. The conductive contact has a top area with a second diameter CD2 for opening the insulation. A patterned dielectric layer, further formed on the metal gates, the insulation and the conductive contact, at least has a first M0 opening with a third diameter CD3 for exposing the conductive contact, wherein CD2>CD3.

Abstract: The present invention provides a manufacturing method of a semiconductor device, at least containing the following steps: first, a substrate is provided, wherein a first dielectric layer is formed on the substrate, at least one metal gate is formed in the first dielectric layer and at least one source drain region (S/D region) is disposed on two sides of the metal gate, at least one first trench is then formed in the first dielectric layer, exposing parts of the S/D region. The manufacturing method for forming the first trench further includes performing a first photolithography process through a first photomask and performing a second photolithography process through a second photomask, and at least one second trench is formed in the first dielectric layer, exposing parts of the metal gate, and finally, a conductive layer is filled in each first trench and each second trench.

Abstract: According to one embodiment of the present invention, a method for forming a semiconductor structure having an opening is provided. First, a substrate is provided, wherein a first region and a second region are defined on the substrate and an overlapping area of the first region and the second region is defined as a third region. Then, a material layer is formed on the substrate. A first hard mask and a second hard mask are formed on the material layer. The first hard mask in the first region is removed to form a patterned first hard mask. The second hard mask in the third region is removed to form a patterned second hard mask. Lastly, the material layer is patterned by using the patterned second hard mask layer as a mask to form at least an opening in the third region only.

Abstract: The present invention provides a manufacturing method of a semiconductor structure, comprising the following steps. First, a substrate is provided, a first dielectric layer is formed on the substrate, a metal gate is disposed in the first dielectric layer and at least one source/drain region (S/D region) is disposed on two sides of the metal gate, a second dielectric layer is then formed on the first dielectric layer, a first etching process is then performed to form a plurality of first trenches in the first dielectric layer and the second dielectric layer, wherein the first trenches expose each S/D region. Afterwards, a salicide process is performed to form a salicide layer in each first trench, a second etching process is then performed to form a plurality of second trenches in the first dielectric layer and the second dielectric layer, and the second trenches expose the metal gate.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a region; forming a gate structure on the region of the substrate; forming a raised epitaxial layer in the substrate adjacent to two sides of the gate structure; covering a dielectric layer on the gate structure and the raised epitaxial layer; and using a planarizing process to partially remove the dielectric layer and the gate structure such that the surface of the gate structure is even with the surface of the raised epitaxial layer.

Abstract: A semiconductor structure includes a metal gate, a second dielectric layer and a contact plug. The metal gate is located on a substrate and in a first dielectric layer, wherein the metal gate includes a work function metal layer having a U-shaped cross- sectional profile and a low resistivity material located on the work function metal layer. The second dielectric layer is located on the metal gate and the first dielectric layer. The contact plug is located on the second dielectric layer and in a third dielectric layer, thereby a capacitor is formed. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.

Abstract: A plug structure including a first dielectric layer, a second dielectric layer, a barrier layer and a second plug is provided. The first dielectric layer having a first plug therein is located on a substrate, wherein the first plug physically contacts a source/drain in the substrate. The second dielectric layer having an opening exposing the first plug is located on the first dielectric layer. The barrier layer conformally covers the opening, wherein the barrier layer has a bottom part and a sidewall part, and the bottom part is a single layer and physically contacts the first plug while the sidewall part is a dual layer. The second plug fills the opening and on the barrier layer. Moreover, a process of forming a plug structure is also provided.

Abstract: A plug structure including a first dielectric layer, a second dielectric layer, a barrier layer and a second plug is provided. The first dielectric layer having a first plug therein is located on a substrate, wherein the first plug physically contacts a source/drain in the substrate. The second dielectric layer having an opening exposing the first plug is located on the first dielectric layer. The barrier layer conformally covers the opening, wherein the barrier layer has a bottom part and a sidewall part, and the bottom part is a single layer and physically contacts the first plug while the sidewall part is a dual layer. The second plug fills the opening and on the barrier layer. Moreover, a process of forming a plug structure is also provided.

Abstract: An embedded resistor including a first interdielectric layer, a cap layer, a resistive layer and a cap film is provided. The first interdielectric layer is located on a substrate. The cap layer is located on the first interdielectric layer, wherein the cap layer has a trench. The resistive layer conformally covers the trench, thereby having a U-shaped cross-sectional profile. The cap film is located in the trench and on the resistive layer, or, an embedded thin film resistor including a first interdielectric layer, a cap layer and a bulk resistive layer is provided. The first interdielectric layer is located on a substrate. The cap layer is located on the first interdielectric layer, wherein the cap layer has a trench. The bulk resistive layer is located in the trench.

Abstract: A static random access memory unit cell layout structure is disclosed, in which a slot contact is disposed on one active area and another one across from the one. A static random access memory unit cell structure and a method of fabricating the same are also disclosed, in which, a slot contact is disposed on drains of a pull-up transistor and a pull-down transistor, and a metal-zero interconnect is disposed on the slot contact and a gate line of another pull-up transistor. Accordingly, there is not an intersection of vertical and horizontal metal-zero interconnects, and there is no place suffering from twice etching. Leakage junction due to stitch recess can be avoided.

Abstract: The present invention provides a method for forming a fin structure comprising the following steps: first, a substrate is provided and a plurality of fin structures, a plurality of first dummy fin structures and a plurality of second dummy fin structures are formed on the substrate; a first patterned photoresist is used as a hard mask to perform a first etching process to remove each first dummy fin structure; then a second patterned photoresist is used as a hard mask to perform a second etching process to remove each second dummy fin structure, wherein the pattern density of the first patterned photoresist is higher than the pattern density of the second patterned.

Abstract: The present invention provides a method for forming a semiconductor structure having a metal connect. A substrate is provided, and a transistor and a first ILD layer are formed thereon. A first contact plug is formed in the first ILD layer to electrically connect the source/drain region. A second ILD layer and a third ILD layer are formed on the first ILD layer. A first opening above the gate and a second opening above the first contact plug are formed, wherein a depth of the first contact plug is deeper than that of the second opening. Next, the first opening and the second opening are deepened. Lastly, a metal layer is filled into the first opening and the second opening to respectively form a first metal connect and a second metal connect.

Abstract: A method of forming a semiconductor structure having at least a contact plug includes the following steps. At first, at least a transistor and an inter-layer dielectric (ILD) layer are formed on a substrate, and the transistor includes a gate structure and two source/drain regions. Subsequently, a cap layer is formed on the ILD layer and on the transistor, and a plurality of openings that penetrate through the cap layer and the ILD layer until reaching the source/drain regions are formed. Afterward, a conductive layer is formed to cover the cap layer and fill the openings, and a part of the conductive layer is further removed for forming a plurality of first contact plugs, wherein a top surface of a remaining conductive layer and a top surface of a remaining cap layer are coplanar, and the remaining cap layer totally covers a top surface of the gate structure.

Abstract: A method for fabricating fin-shaped field-effect transistor (FinFET) is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure on the substrate; forming a first gate structure on the fin-shaped structure; forming a first epitaxial layer in the fin-shaped structure adjacent to the first gate structure; forming an interlayer dielectric layer on the first gate structure and the first epitaxial layer; forming an opening in the interlayer dielectric layer to expose the first epitaxial layer; forming a silicon cap on the first epitaxial layer; and forming a contact plug in the opening.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a region; forming a gate structure on the region of the substrate; forming a raised epitaxial layer in the substrate adjacent to two sides of the gate structure; covering a dielectric layer on the gate structure and the raised epitaxial layer; and using a planarizing process to partially remove the dielectric layer and the gate structure such that the surface of the gate structure is even with the surface of the raised epitaxial layer.

Abstract: The present invention provides a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate. The present invention further provides a method of making the same.

Abstract: The present invention provides a method for forming a semiconductor structure having a metal connect. A substrate is provided, and a transistor and a first ILD layer are formed thereon. A first contact plug is formed in the first ILD layer to electrically connect the source/drain region. A second ILD layer and a third ILD layer are formed on the first ILD layer. A first opening above the gate and a second opening above the first contact plug are formed, wherein a depth of the first contact plug is deeper than that of the second opening. Next, the first opening and the second opening are deepened. Lastly, a metal layer is filled into the first opening and the second opening to respectively form a first metal connect and a second metal connect.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a region; a gate structure disposed on the region of the substrate; a raised epitaxial layer disposed in the substrate adjacent to two sides of the gate structure, wherein the surface of the raised epitaxial layer is even with the surface of the gate structure.

Abstract: The present invention provides a semiconductor structure including at least a contact plug. The structure includes a substrate, a transistor, a first ILD layer, a second ILD layer and a first contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor and levels with a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The first contact plug is disposed in the first ILD layer and the second ILD layer and includes a first trench portion and a first via portion, wherein a boundary of the first trench portion and a first via portion is higher than the top surface of the gate. The present invention further provides a method of making the same.

Abstract: A manufacturing method for a semiconductor device includes providing a substrate having at least a gate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.